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ORCIDFPT 2018: Naha, Japan
- International Conference on Field-Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December 10-14, 2018. IEEE 2018, ISBN 978-1-7281-0214-6
Invited Speaker
- Hiroshi Miyata:
Digital Transformation of Automobile and Mobility Service. 1-5
Oral Session 1: Neural Networks
- Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
:
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. 6-13 - Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk:
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. 14-21 - Mike Strickland:
FPGA Accelerated HPC and Data Analytics. 21 - Benjamin Morcos, Terrence C. Stewart, Chris Eliasmith, Nachiket Kapre:
Implementing NEF Neural Networks on Embedded FPGAs. 22-29 - Hideharu Amano:
Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs. 22 - Kees A. Vissers:
Novel Neural Network Applications on New Python Enabled Platforms. 23 - Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. 30-37
Oral Session 2: High Level Synthesis
- Anuj Vaishnav, Khoa Dang Pham, Dirk Koch:
Live Migration for OpenCL FPGA Accelerators. 38-45 - Ahmed Sanaullah, Rushi Patel, Martin C. Herbordt:
An Empirically Guided Optimization Framework for FPGA OpenCL. 46-53 - Jing Chen, Xue Liu, Jason Helge Anderson:
Software-Specified FPGA Accelerators for Elementary Functions. 54-61 - Leandro de Souza Rosa, Vanderlei Bonato, Christos-Savvas Bouganis:
Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach. 62-69 - Jaume Bosch, Xubin Tan, Antonio Filgueras, Miquel Vidal, Marc Mateu, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta:
Application Acceleration on FPGAs with OmpSs@FPGA. 70-77
Oral Session 3: Stream Processing
- Philippos Papaphilippou, Chris Brooks, Wayne Luk:
FLiMS: Fast Lightweight Merge Sorter. 78-85 - Makoto Saitoh, Kenji Kise:
Very Massive Hardware Merge Sorter. 86-93 - Phong Tran, Thinh Hung Pham, Siew Kei Lam, Meiqing Wu, Bhavan A. Jasani:
Stream-Based ORB Feature Extractor with Dynamic Power Optimization. 94-101 - Oscar Rahnama, Tommaso Cavallari, Stuart Golodetz, Simon Walker, Philip H. S. Torr:
R3SGM: Real-Time Raster-Respecting Semi-Global Matching for Power-Constrained Systems. 102-109
Oral Session 4: Design Methodologies and Tools
- Kevin E. Murray, Vaughn Betz:
Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization. 110-117 - Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde:
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. 118-125 - Kuang Ping Niu, Jason Helge Anderson:
Compact Area and Performance Modelling for CGRA Architecture Evaluation. 126-133
Oral Session 5: Networking and Data Applications
- Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani:
MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories. 134-141 - Yunhui Qiu, Hankun Lv, Jinyu Xie, Wenbo Yin, Lingli Wang:
Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA. 142-149 - Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
A Nearest Neighbor Search Engine Using Distance-Based Hashing. 150-157 - Siddhartha, Nachiket Kapre:
DaCO: A High-Performance Token Dataflow Coprocessor Overlay for FPGAs. 158-165 - Nadeen Gebara, Jiuxi Meng, Wayne Luk, Paolo Costa:
Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey. 166-173
Oral Session 6: Security and Dependability
- Thibaut Marty, Tomofumi Yuki, Steven Derrien:
Enabling Overclocking Through Algorithm-Level Error Detection. 174-181 - Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, Christophe Bobda:
Secure Hardware Kernels Execution in CPU+FPGA Heterogeneous Cloud. 182-189 - Farnoud Farahmand, Malik Umar Sharif, Kevin Briggs, Kris Gaj:
A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES. 190-197 - Shane T. Fleming, David B. Thomas:
Injecting FPGA Configuration Faults in Parallel. 198-205
Oral Session 7: FPGA Architectures
- Tian Tan, Eriko Nurvitadhi, David Shih, Derek Chiou:
Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks. 206-213 - Jin Hee Kim, Jongeun Lee, Jason Helge Anderson:
FPGA Architecture Enhancements for Efficient BNN Implementation. 214-221 - Brett Grady, Jason Helge Anderson:
Synthesizable Heterogeneous FPGA Fabrics. 222-229
Poster Papers
- Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar:
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning. 230-233 - Jakub Cabal, Lukás Kekely, Jan Korenek:
High-Speed Computation of CRC Codes for FPGAs. 234-237 - Xianchao Xu, Brian Liu:
FCLNN: A Flexible Framework for Fast CNN Prototyping on FPGA with OpenCL and Caffe. 238-241 - Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung:
Accelerating Top-k ListNet Training for Ranking Using FPGA. 242-245 - Yu Zou, Mingjie Lin:
GridGAS: An I/O-Efficient Heterogeneous FPGA+CPU Computing Platform for Very Large-Scale Graph Analytics. 246-249 - Bowen P. Y. Kwan, Gary C. T. Chow, Tim Todman, Wayne Luk, Wenguang Xu:
Lossy Multiport Memory. 250-253 - Takuya Yamazaki, Tsutomu Maruyama:
An FPGA Implementation of Robust Matting. 254-257 - Sadegh Yazdanshenas, Vaughn Betz:
Improving Confidentiality in Virtualized FPGAs. 258-261 - Naohito Nakasato, Hiroshi Daisaka, Tadashi Ishikawa:
High Performance High-Precision Floating-Point Operations on FPGAs Using OpenCL. 262-265 - Tobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck:
Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs. 266-269 - Kento Tajiri, Tsutomu Maruyama:
FPGA Acceleration of a Supervised Learning Method for Hyperspectral Image Classification. 270-273 - Liang Xie, Xitian Fan, Wei Cao, Lingli Wang:
High Throughput CNN Accelerator Design Based on FPGA. 274-277 - Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck:
Hardware-Accelerated Index Construction for Semantic Web. 278-281 - Qiangpu Chen, Minghua Shen, Nong Xiao:
DP-Pack: Distributed Parallel Packing for FPGAs. 282-285 - Dennis R. E. Gnad, Sascha Rapp, Jonas Krautter, Mehdi Baradaran Tahoori:
Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs. 286-289 - Hossein Omidian, Nick Ivanov, Guy G. F. Lemieux:
An Accelerated OpenVX Overlay for Pure Software Programmers. 290-293 - André Bannwart Perina, Vanderlei Bonato:
Mapping Estimator for OpenCL Heterogeneous Accelerators. 294-297 - Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. 298-301 - Krystine Dawn Sherwin, Ben Stappers, Prabu Thiagaraj, Kevin I-Kai Wang, Oliver Sinnen:
Investigating How Hardware Architectures are Expressed in High-Level Languages for an SKA Algorithm. 302-305 - Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong:
Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. 306-309 - Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara:
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. 310-313 - Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker:
Performance Estimation for Exascale Reconfigurable Dataflow Platforms. 314-317 - Teng Yu, Bo Feng, Mark Stillwell, Liucheng Guo, Yuchun Ma, John Thomson:
Lattice-Based Scheduling for Multi-FPGA Systems. 318-321 - Emmanouil Pissadakis, Nikolaos Alachiotis, Panagiotis Skrimponis, Dimitris Theodoropoulos, Thanasis Korakis, Dionisios N. Pnevmatikatos:
ReFiRe: Efficient Deployment of Remote Fine-Grained Reconfigurable Accelerators. 322-325 - Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. 326-329 - Farnoud Farahmand, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
Face-off Between the CAESAR Lightweight Finalists: ACORN vs. Ascon. 330-333 - Kristiyan Manev, Dirk Koch:
Large Utility Sorting on FPGAs. 334-337 - Dionysios Diamantopoulos, Christoph Hagleitner:
A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping. 338-341 - Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews:
Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers. 342-345 - Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao:
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. 346-349 - Robert Hale, Brad L. Hutchings:
Distributed-Memory Based FPGA Debug: Design Timing Impact. 350-353 - Matthew B. Ashcraft, Jeffrey Goeders:
Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs. 354-357 - Haomiao Wang, Ben Stappers, Prabu Thiagaraj, Oliver Sinnen:
Optimisation of Convolution of Multiple Different Sized Filters in SKA Pulsar Search Engine. 358-361 - Jia Liu, Qiang Liu:
Speed and Resource Optimization of BFGS Quasi-Newton Implementation on FPGA Using Inexact Line Search Method for Neural Network Training. 362-365 - Alexander Kroh, Oliver Diessel:
A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms. 366-369
PhD Forum Papers
- Yu Xie, He Chen, Yizhuang Xie, Chuang-An Mao, Bingyi Li:
An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDIC. 370-373 - Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. 374-377 - Antoniette Mondigo, Kentaro Sano, Hiroyuki Takizawa:
Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs. 378-380
Demonstration Papers
- Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus:
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. 381-384 - Donald G. Bailey, Yuan Chang, Steven Le Moan:
Lens Distortion Self-Calibration Using the Hough Transform. 385-388 - Shaoxia Fang, Lu Tian, Junbin Wang, Shuang Liang, Dongliang Xie, Zhongmin Chen, Lingzhi Sui, Qian Yu, Xiaoming Sun, Yi Shan, Yu Wang:
Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks. 389-392 - Daniel Holanda Noronha, Kahlan Gibson, Bahar Salehpour, Steven J. E. Wilton:
LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs. 393-396
FPGA Design Competition
- Kyosuke Mori, Yuuki Saitoh, Naohito Nakasato:
Introduction of MNSTbot. 397-399 - Musashi Aoto, Yasutaka Wada, Yousuke Numata:
Development of an FPGA Controlled "Mini-Car" Toward Autonomous Driving. 400-402 - Yuya Kudo, Atsushi Takada, Soji Tsuda, Takumi Sakai, Tomonori Izumi:
A Platform on All-Programmable SoC for Micro Autonomous Robots. 403-406 - Yohei Shimmyo, Maiko Arakawa, Shunsuke Mie, Hiroaki Saito, Yuichi Okuyama, Hiroki Yomogita:
Implementation of an Autonomous Driving System for FPT2018 FPGA Design Competition Using the Zynqberry Processing Board. 407-410 - Akira Kojima, Yohei Nose:
Development of an Autonomous Driving Robot Car Using FPGA. 411-414 - Hiromichi Wakatsuki, Takao Kido, Kenta Arai, Yuhei Sugata, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa:
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA. 415-418 - Hiroki Bingo:
Development of a Control Target Recognition for Autonomous Vehicle Using FPGA with Python. 419-420 - Yasuhiro Nitta, Sou Tamura, Hideki Takase:
A Study on Introducing FPGA to ROS Based Autonomous Driving System. 421-424 - Kaijie Wei, Koki Honda, Hideharu Amano:
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks. 425-428
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