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ORCIDIlias Chlis
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2020 – today
- 2021
[j8]Jay Im
, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. IEEE J. Solid State Circuits 56(1): 7-18 (2021)- 2020
- [c3]Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. ISSCC 2020: 116-118
2010 – 2019
- 2018
- [j7]Domenico Pepe, Ilias Chlis, Domenico Zito:
Transformer-Based Input Integrated Matching in Cascode Amplifiers: Analytical Proofs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1495-1504 (2018) - [c2]James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits 2018: 47-48 - 2017
- [j6]Ilias Chlis, Domenico Pepe, Domenico Zito:
Transformer-coupled π-network differential CMOS oscillator circuit topology. Int. J. Circuit Theory Appl. 45(3): 407-418 (2017) - [j5]Ilias Chlis, Domenico Pepe, Domenico Zito:
Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology. Int. J. Circuit Theory Appl. 45(12): 1993-2016 (2017) - 2016
- [j4]Ilias Chlis, Domenico Pepe, Domenico Zito:
Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology. Int. J. Circuit Theory Appl. 44(3): 616-638 (2016) - [j3]Ilias Chlis, Domenico Pepe, Domenico Zito:
Phase noise analysis in CMOS differential Armstrong oscillator topology. Int. J. Circuit Theory Appl. 44(9): 1697-1705 (2016) - [j2]Domenico Pepe, Ilias Chlis, Domenico Zito:
67 GHz three-spiral transformer CMOS oscillator. Int. J. Circuit Theory Appl. 44(10): 1798-1813 (2016) - 2015
- [j1]Ilias Chlis, Domenico Pepe, Domenico Zito:
Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair. J. Circuits Syst. Comput. 24(4): 1550052:1-1550052:18 (2015) - 2012
- [c1]Athanasios Dimakos, Matthias Bucher, Rupendra Kumar Sharma, Ilias Chlis:
Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion. ICECS 2012: 17-20
Coauthor Index
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