"A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC ..."

James Hudner et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502436

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-30

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James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits 2018: 47-48

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