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ORCIDYing Cao 0010
Person information
- affiliation: Xilinx, Inc., San Jose, CA, USA
Other persons with the same name
- Ying Cao — disambiguation page
- Ying Cao 0001
![[0000-0002-9288-3167]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9288-3167")
— City University of Hong Kong, Hong Kong, SAR, China - Ying Cao 0002 — Kitami Institute of Technology, Hokkaido, Japan
- Ying Cao 0003 — Xidian Universiy, Xi'an, China
- Ying Cao 0004 — China University of Geosciences, Wuhan, China
- Ying Cao 0005 — University at Buffalo, SUNY, Buffalo, NY, USA
- Ying Cao 0006 — SKLOIS, Institute of Information Engineering, Chinese Academy of Sciences, Beijing, China
- Ying Cao 0007 — Hong Kong University of Science and Technology, Hong Kong, SAR, China
- Ying Cao 0008 — Belgian Nuclear Research Centre, Mol, Belgium (and 1 more)
- Ying Cao 0009 — Beijing Institute of Geology, Beijing, China
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2020 – today
- 2023
[c4]Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans:
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. ISSCC 2023: 204-205- 2022
- [j2]Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans:
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. IEEE J. Solid State Circuits 57(4): 1199-1210 (2022) - 2021
- [j1]Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. IEEE J. Solid State Circuits 56(1): 7-18 (2021) - [c3]Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans:
A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. VLSI Circuits 2021: 1-2 - 2020
- [c2]Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. ISSCC 2020: 116-118
2010 – 2019
- 2018
- [c1]Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang:
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. ISSCC 2018: 378-380
Coauthor Index
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