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2020 – today
- 2021
[c10]Naftali Weiss, Gregory Cooke, Peter Schvan, Pascal Chevalier, Andreia Cathelin, Sorin P. Voinigescu:
200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator. ESSCIRC 2021: 483-486- 2020
- [j10]Christian Schmidt
, Hiroshi Yamazaki, Gregory Raybon, Peter Schvan, Erwan Pincemin, S. J. Ben Yoo, Daniel J. Blumenthal, Takayuki Mizuno, Robert Elschner:
Data Converter Interleaving: Current Trends and Future Perspectives. IEEE Commun. Mag. 58(5): 19-25 (2020)
2010 – 2019
- 2019
- [j9]Alireza Zandieh, Peter Schvan, Sorin P. Voinigescu:
Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications. IEEE J. Solid State Circuits 54(9): 2375-2387 (2019) - [c9]Sebastien Blais, Yuriy M. Greshishchev, Peter Schvan, Ian Betty, Douglas McGhan:
Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges. BCICTS 2019: 1-6 - 2018
- [c8]Alireza Zandieh, Peter Schvan, Sorin P. Voinigescu:
A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications. BCICTS 2018: 52-55 - 2016
- [j8]James Hoffman, Stefan Shopov, Pascal Chevalier, Andreia Cathelin, Peter Schvan, Sorin P. Voinigescu:
55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters. IEEE J. Solid State Circuits 51(9): 2040-2053 (2016) - 2011
- [j7]Ricardo Andres Aroca, Peter Schvan, Sorin P. Voinigescu:
A 2.4-Vpp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies. IEEE J. Solid State Circuits 46(10): 2226-2239 (2011) - [c7]Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan:
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. ISSCC 2011: 194-196 - 2010
- [c6]Samira Bashiri, Calvin Plett, Jorge Aguirre, Peter Schvan:
A 40 Gb/s transimpedance amplifier in 65 nm CMOS. ISCAS 2010: 757-760 - [c5]Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang:
A 40GS/s 6b ADC in 65nm CMOS. ISSCC 2010: 390-391
2000 – 2009
- 2009
- [c4]Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt:
Clock recovery for a 40 Gb/s QPSK optical receiver. ICECS 2009: 695-698 - 2008
- [c3]Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski:
A 24GS/s 6b ADC in 90nm CMOS. ISSCC 2008: 544-545 - 2007
- [j6]Terry Yao, Michael Q. Gordon, Keith K. W. Tang, Kenneth H. K. Yau, Ming-Ta Yang, Peter Schvan, Sorin P. Voinigescu:
Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio. IEEE J. Solid State Circuits 42(5): 1044-1057 (2007) - [j5]Theodoros Chalvatzis, Kenneth H. K. Yau, Ricardo Andres Aroca, Peter Schvan, Ming-Ta Yang, Sorin P. Voinigescu:
Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS. IEEE J. Solid State Circuits 42(7): 1564-1573 (2007) - [c2]Sorin P. Voinigescu, Sean T. Nicolson, Mehdi Khanpour, Keith K. W. Tang, Kenneth H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, George V. Eleftheriades, Peter Schvan, Ming-Ta Yang:
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples. ISCAS 2007: 1971-1974 - 2006
- [c1]Peter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben-Hamida:
A 22GS/s 5b adc in 0.13µm SiGe BiCMOS. ISSCC 2006: 2340-2349 - 2000
- [j4]Yuriy M. Greshishchev, Peter Schvan:
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application. IEEE J. Solid State Circuits 35(9): 1353-1359 (2000) - [j3]Yuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers:
A fully integrated SiGe receiver IC for 10-Gb/s data rate. IEEE J. Solid State Circuits 35(12): 1949-1957 (2000)
1990 – 1999
- 1999
- [j2]Yuriy M. Greshishchev, Peter Schvan:
A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier. IEEE J. Solid State Circuits 34(12): 1914-1920 (1999) - 1997
- [j1]Sorin P. Voinigescu, Michael C. Maliepaard, Jonathan L. Showell, Greg E. Babcock, David Marchesan, Michael Schroter, Peter Schvan, David L. Harame:
A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid State Circuits 32(9): 1430-1439 (1997)
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