"Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS."

Theodoros Chalvatzis et al. (2007)

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DOI: 10.1109/JSSC.2007.899093

access: closed

type: Journal Article

metadata version: 2020-08-30

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Theodoros Chalvatzis, Kenneth H. K. Yau, Ricardo Andres Aroca, Peter Schvan, Ming-Ta Yang, Sorin P. Voinigescu:
Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS. IEEE J. Solid State Circuits 42(7): 1564-1573 (2007)

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