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Journal Articles
- 2022
[j2]James Bailey
, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto:
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. IEEE J. Solid State Circuits 57(1): 32-43 (2022)- 2003
- [j1]David Cassan, John R. Long:
A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS. IEEE J. Solid State Circuits 38(3): 427-435 (2003)
Conference and Workshop Papers
- 2021
- [c6]James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan:
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. ISSCC 2021: 140-142 - 2019
- [c5]Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto:
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC 2019: 482-484 - 2014
- [c4]Chris D. Holdenried, Ryan Bespalko, Marcus van Ierssel, Mehrdad Ramezani, David Cassan, Siamak Sarvari, Saman Sadr:
Performance of edge tap decision feedback equalization methods for wireline receivers. NEWCAS 2014: 5-8 - 2012
- [c3]Kamran Farzan, Mehrdad Ramezani, Angus McLaren, Roman Pahuta, Nadeesha Amarasinghe, David Cassan, Saman Sadr:
A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. ESSCIRC 2012: 225-228 - 2011
- [c2]Mehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr:
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. ISSCC 2011: 352-354 - 2002
- [c1]David Cassan, John R. Long:
A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 μm CMOS. CICC 2002: 419-422
Coauthor Index
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