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Angus McLaren
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2020 – today
- 2021
- [c6]Ravi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren:
11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. ISSCC 2021: 181-183
2010 – 2019
- 2018
- [c5]Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr:
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. ISSCC 2018: 106-108 - 2012
- [c4]Kamran Farzan, Mehrdad Ramezani, Angus McLaren, Roman Pahuta, Nadeesha Amarasinghe, David Cassan, Saman Sadr:
A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. ESSCIRC 2012: 225-228 - 2011
- [c3]Mehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr:
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. ISSCC 2011: 352-354
2000 – 2009
- 2001
- [j1]Angus McLaren, Ken Martin:
Generation of accurate on-chip time constants and stable transconductances. IEEE J. Solid State Circuits 36(4): 691-695 (2001) - 2000
- [c2]Angus McLaren, Kenneth W. Martin:
Generation of accurate on-chip time-constants using a monolithic CMOS PLL with hybrid analog and digital control. ISCAS 2000: 257-260
1990 – 1999
- 1999
- [c1]G. P. Hartman, Kenneth W. Martin, Angus McLaren:
Continuous-time adaptive-analog coaxial cable equalizer in 0.5 um CMOS. ISCAS (2) 1999: 97-100
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