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2020 – today
- 2024
[j8]Wookjin Shin, Hyeongmin Seo
, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han:
A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1819-1823 (2024)
2010 – 2019
- 2013
- [j7]Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim:
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 268-278 (2013) - [j6]Young-Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim:
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 303-313 (2013) - [j5]Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim:
10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2080-2093 (2013) - 2012
- [j4]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile. IEEE J. Solid State Circuits 47(5): 1199-1208 (2012) - 2011
- [j3]Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong:
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46(11): 2560-2570 (2011) - [c5]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS. ISSCC 2011: 360-362 - 2010
- [j2]Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 120-125 (2010)
2000 – 2009
- 2009
- [c4]Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, ByeongHa Park, Chulwoo Kim:
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. CICC 2009: 243-246 - 2008
- [c3]Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A slew-rate controlled output driver with one-cycle tuning time. ASP-DAC 2008: 99-100 - 2007
- [c2]Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim:
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver. ISSCC 2007: 408-611 - 2006
- [j1]Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim:
A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. IEEE J. Solid State Circuits 41(9): 2077-2082 (2006) - 2005
- [c1]Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim:
Differential Pass Transistor Pulsed Latch. SoCC 2005: 295-300
Coauthor Index
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