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ORCIDRamin Farjad-Rad
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2020 – today
- 2021
[j10]Shahab Ardalan, Ramin Farjadrad, Mark Kuemerle, Ken Poulton, Suresh Subramaniam, Bapiraju Vinnakota:
An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW). IEEE Micro 41(1): 54-60 (2021)- [c10]Ramin Farjadrad, Kambiz Kaviani, David Nguyen, Michael Brown, Govert Geelen, Corné Bastiaansen, Narendra Rao, Viswa Popuri, Greg Shen, Hamid Khatibi, Saudas Dey, Anirban Chatterjee, David Shen, Peter Zijlstra, Harrie Gunnink, Kebin Zhang, Venkat Penumuchu, Oliver Weiss, Edward J. F. Paulus, Joost Briaire:
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS. ISSCC 2021: 194-196 - 2020
- [j9]Ramin Farjadrad, Mark Kuemerle, Bapi Vinnakota:
A Bunch-of-Wires (BoW) Interface for Interchiplet Communication. IEEE Micro 40(1): 15-24 (2020) - [c9]Shahab Ardalan, Halil Cirit, Ramin Farjad-Rad, Mark Kuemerle, Ken Poulton, Suresh Subramanian, Bapiraju Vinnakota:
Bunch of Wires: An Open Die-to-Die Interface. Hot Interconnects 2020: 9-16
2010 – 2019
- 2019
- [c8]Greg Taylor, Ramin Farjadrad, Bapiraju Vinnakota:
High Capacity On-Package Physical Link Considerations. Hot Interconnects 2019: 19-22 - [c7]Ramin Farjadrad, Bapiraju Vinnakota:
A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication. Hot Interconnects 2019: 27-273 - 2015
- [c6]Ramin Shirani, Ramin Farjad-Rad:
10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference. Hot Chips Symposium 2015: 1-27 - 2012
- [j8]Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng:
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits 47(12): 3261-3272 (2012) - [c5]Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani:
A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC 2012: 412-413 - 2011
- [c4]Ramin Shirani, Ramin Farjadrad:
Low-power high-density 10GBASE-T ethernet transceiver. Hot Chips Symposium 2011: 1-20
2000 – 2009
- 2007
- [c3]Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner
, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe:
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. ISSCC 2007: 228-599 - 2004
- [j7]Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng:
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits 39(9): 1553-1561 (2004) - 2003
- [j6]Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan:
Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits 38(4): 614-621 (2003) - [j5]Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan:
A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits 38(12): 2101-2110 (2003) - [c2]Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran:
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC 2003: 77-80 - [c1]Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton:
CMOS High-Speed I/Os - Present and Future. ICCD 2003: 454-461 - 2002
- [j4]Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton:
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits 37(12): 1804-1812 (2002) - 2000
- [j3]Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. IEEE J. Solid State Circuits 35(5): 757-764 (2000)
1990 – 1999
- 1999
- [j2]Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. IEEE J. Solid State Circuits 34(5): 580-585 (1999) - 1998
- [j1]Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz:
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. IEEE J. Solid State Circuits 33(5): 713-722 (1998)
Coauthor Index
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