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ORCIDYiwen Wang 0003
Person information
- affiliation: Feng Chia University, Taichung
Other persons with the same name
- Yiwen Wang — disambiguation page
- Yiwen Wang 0001 — Eindhoven University of Technology, The Netherlands
- Yiwen Wang 0002
![[0000-0002-1878-6182]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-1878-6182")
— Hong Kong University of Science and Technology (and 2 more) - Yiwen Wang 0004 — Central South University, Changsha, School of Software
- Yiwen Wang 0005 — Tokyo Institute Of Technology, Department of Communications and Integrated Systems
- Yiwen Wang 0006 — Michigan State University, East Lansing, Department of Electrical and Computer Engineering
- Yiwen Wang 0007 — University of Copenhagen, Department of Computer Science, Denmark
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2010 – 2019
- 2010
[c10]Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang, Yiwen Wang:
Application Specific Instruction Set Exploration on VLIW Architectures. ESA 2010: 105-108
2000 – 2009
- 2008
- [c9]Chijie Lin, Jiying Wu, Jerung Shiu, Chiuyun Hung, De-Sheng Chen, Yiwen Wang:
Performance Improvement using Application-Specific Instructions under Hardware Constraints. ICESS 2008: 459-463 - [c8]Jiying Wu, Chijie Lin, Desheng Chen, Yiwen Wang:
Memory Models for an Application-Specific Instruction-set Processor Design Flow. ICESS 2008: 471-478 - 2007
- [j2]De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng:
Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. Artif. Intell. 20(6): 821-830 (2007) - [c7]Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng:
Noise-Aware Floorplanning for Fast Power Supply Network Design. ISCAS 2007: 2028-2031 - [c6]Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Yiwen Wang:
Application-Specific Instruction Generation for SOC Processors. ISCAS 2007: 3752-3755 - 2006
- [j1]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. J. Circuits Syst. Comput. 15(1): 107-128 (2006) - 2005
- [c5]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang, Hsin-Hsien Ho:
Modem floorplanning with abutment and fixed-outline constraints. ISCAS (6) 2005: 6214-6217 - 2004
- [c4]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
Robust fixed-outline floorplanning through evolutionary search. ASP-DAC 2004: 42-44 - [c3]Ching-Chung Hu, De-Sheng Chen, Yiwen Wang:
Fast multilevel floorplanning for large scale modules. ISCAS (5) 2004: 205-208 - 2003
- [c2]De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang:
Non-slicing floorplans with boundary constraints using generalized polish expression. ASP-DAC 2003: 342-345 - 2002
- [c1]Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
GPE: A New Representation for VLSI Floorplan Problem. ICCD 2002: 42-44
Coauthor Index
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