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ORCIDRenzhi Liu
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j8]Hongru Ren
, Renzhi Liu, Zhijian Cheng, Hui Ma, Hongyi Li:
Data-Driven Event-Triggered Control for Nonlinear Multi-Agent Systems With Uniform Quantization. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 712-716 (2024)- [c10]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent R. Carlton:
A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j7]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton:
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. IEEE J. Solid State Circuits 58(4): 1037-1050 (2023) - [j6]Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton:
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks. IEEE J. Solid State Circuits 58(5): 1285-1298 (2023) - [j5]Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent R. Carlton:
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. IEEE J. Solid State Circuits 58(10): 2826-2838 (2023) - [j4]Chaoxu Luan, Renzhi Liu, Jing Sun, Shangren Su, Zhenyao Shen:
An Improved Future Land-Use Simulation Model with Dynamically Nested Ecological Spatial Constraints. Remote. Sens. 15(11): 2921 (2023) - 2022
- [c9]Xiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran, Zakir Ahmed, Nachiket V. Desai, Nicolas Butzen, James W. Tschanz, Vivek De:
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. ISSCC 2022: 478-480 - [c8]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu:
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. VLSI Technology and Circuits 2022: 36-37 - 2020
- [j3]Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Deepak Dasalukunte, Vinod Kristem, Mario A. Santana Lopez, Alexander W. Min, Shahrnaz Azizi, Minyoung Park, Brent R. Carlton:
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration. IEEE J. Solid State Circuits 55(5): 1151-1164 (2020)
2010 – 2019
- 2019
- [c7]Richard Dorrance, Renzhi Liu, K. T. Asma Beevi, Deepak Dasalukunte, Mario A. Santana Lopez, Vinod Kristem, Shahrnaz Azizi, Brent R. Carlton:
An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba. VLSI Circuits 2019: 80- - 2018
- [c6]Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De:
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC 2018: 46-48 - 2017
- [c5]Mehmet Meric Isgenc, Samuel Pagliarini, Renzhi Liu, Larry T. Pileggi:
Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs. ISQED 2017: 180-185 - 2016
- [j2]Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. Integr. 52: 185-194 (2016) - [c4]Renzhi Liu, Jeffrey A. Weldon, Larry T. Pileggi:
Extended statistical element selection: a calibration method for high resolution in analog/RF designs. DAC 2016: 104:1-104:6 - [i1]Renzhi Liu:
Digital Calibration Method for High Resolution in Analog/RF Designs. CoRR abs/1606.05903 (2016) - 2015
- [j1]Renzhi Liu, Larry T. Pileggi:
Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 651-655 (2015) - 2014
- [c3]Renzhi Liu, Larry T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with >80 dB harmonic rejection ratio. CICC 2014: 1-4 - [c2]Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi:
Building trusted ICs using split fabrication. HOST 2014: 1-6 - [c1]Kaushik Vaidyanathan, Renzhi Liu, Huseyin Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
Efficient and secure intellectual property (IP) design with split fabrication. HOST 2014: 13-18
Coauthor Index
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