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2020 – today
- 2024
[c12]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent R. Carlton:
A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. VLSI Technology and Circuits 2024: 1-2- 2023
- [j6]Hechen Wang
, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton:
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. IEEE J. Solid State Circuits 58(4): 1037-1050 (2023) - [j5]Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton:
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks. IEEE J. Solid State Circuits 58(5): 1285-1298 (2023) - [j4]Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent R. Carlton:
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. IEEE J. Solid State Circuits 58(10): 2826-2838 (2023) - 2022
- [c11]Jun Chen, Weng-Keen Wong, Bechir Hamdaoui, Abdurrahman Elmaghbub, Kathiravetpillai Sivanesan, Richard Dorrance, Lily L. Yang:
An Analysis of Complex-Valued CNNs for RF Data-Driven Wireless Device Classification. ICC 2022: 4318-4323 - [c10]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu:
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. VLSI Technology and Circuits 2022: 36-37 - [i2]Jun Chen, Weng-Keen Wong, Bechir Hamdaoui, Abdurrahman Elmaghbub, Kathiravetpillai Sivanesan, Richard Dorrance, Lily L. Yang:
An Analysis of Complex-Valued CNNs for RF Data-Driven Wireless Device Classification. CoRR abs/2202.09777 (2022) - [i1]Andrey Belogolovy, Deepak Dasalukunte, Richard Dorrance, Evgeny Stupachenko, Xue Zhang:
Low latency communication over commercially available LTE and remote driving. CoRR abs/2209.09794 (2022) - 2021
- [j3]Deepak Dasalukunte, Richard Dorrance, Le Liang, Lu Lu:
A Vector Processor for Mean Field Bayesian Channel Estimation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1348-1359 (2021) - 2020
- [j2]Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Deepak Dasalukunte, Vinod Kristem, Mario A. Santana Lopez, Alexander W. Min, Shahrnaz Azizi, Minyoung Park, Brent R. Carlton:
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration. IEEE J. Solid State Circuits 55(5): 1151-1164 (2020) - [c9]Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang:
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. FPL 2020: 341-346
2010 – 2019
- 2019
- [c8]Richard Dorrance, Renzhi Liu, K. T. Asma Beevi, Deepak Dasalukunte, Mario A. Santana Lopez, Vinod Kristem, Shahrnaz Azizi, Brent R. Carlton:
An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba. VLSI Circuits 2019: 80- - 2018
- [j1]Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano:
802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53(5): 1411-1422 (2018) - [c7]Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De:
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC 2018: 46-48 - 2016
- [c6]Richard Dorrance, Dejan Markovic:
A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT. VLSI Circuits 2016: 1-2 - 2015
- [b1]Richard Dorrance:
An Energy-Efficient Sparse-BLAS Coprocessor using STT-MRAM. University of California, Los Angeles, USA, 2015 - 2014
- [c5]Richard Dorrance, Fengbo Ren, Dejan Markovic:
A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs. FPGA 2014: 161-170 - 2013
- [c4]Fengbo Ren, Richard Dorrance, Wenyao Xu, Dejan Markovic:
A single-precision compressive sensing signal reconstruction engine on FPGAs. FPL 2013: 1-4 - 2012
- [c3]Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic:
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). ISQED 2012: 275-282 - 2011
- [c2]Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin Hafez, Chih-Kong Ken Yang, Dejan Markovic:
Scalability and design-space analysis of a 1T-1MTJ memory cell. NANOARCH 2011: 32-36 - [c1]Henry Park, Richard Dorrance, Amr Amin Hafez, Fengbo Ren, Dejan Markovic, Chih-Kong Ken Yang:
Analysis of STT-RAM cell design with multiple MTJs per access. NANOARCH 2011: 53-58
Coauthor Index
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