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Shinji Miyano

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shunsuke Okumura

> Home > Persons > Shinji Miyano

Publications

2013
[c18]
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  dblp key:
  - conf/aspdac/YoshimotoTOSMKY13
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  persistent URL:
  - https://dblp.org/rec/conf/aspdac/YoshimotoTOSMKY13
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78
2012
[j9]
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  dblp key:
  - journals/ieiceee/YoshimotoTOSMKY12
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  - https://dblp.org/rec/journals/ieiceee/YoshimotoTOSMKY12
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9(12): 1023-1029 (2012)
[j7]
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  dblp key:
  - journals/ieicet/YoshimotoTOSMKY12
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  - https://dblp.org/rec/journals/ieicet/YoshimotoTOSMKY12
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. 95-C(4): 572-578 (2012)
[c15]
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  dblp key:
  - conf/islped/YoshimotoTUOKSMMKY12
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  - https://dblp.org/rec/conf/islped/YoshimotoTUOKSMMKY12
Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90
[c14]
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  dblp key:
  - conf/isqed/TeradaYOSMKY12
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  - https://dblp.org/rec/conf/isqed/TeradaYOSMKY12
Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492

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