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ORCID"A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation ..."
Shusuke Yoshimoto et al. (2013)
- Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78
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