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ORCIDVLSI 1993: Grenoble, France
- Kakayuki Yanagawa, Peter A. Ivey:
VLSI 93, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September, 1993. IFIP Transactions A-42, North-Holland 1994, ISBN 0-444-89911-1
Keynote
- Joseph Borel, J. Monnier, Gérard Matheron:
The single chip system era. VLSI 1993: 3-12
Layout Synthesis
- Daniel R. Brasen, Arnold Ginetti:
Post-placement technology mapping. VLSI 1993: 15-24 - Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Takashi Kambe:
Optimal layout recycling based on graph theoretic linear programming approach. VLSI 1993: 25-34 - Kim-Minh Nguyen, Martin C. Lefebvre:
A family of module generators for the layout synthesis of I/O buffers. VLSI 1993: 35-44 - Lorenz Ladage, Georg Lodde:
A 45° compaction algorithm handling overconstraints. VLSI 1993: 45-54
Special Purpose Architectures
- Hermann Hauser:
Personal Communicators: A better way to stay in touch. VLSI 1993: 57-61 - Imed Moussa, Ali Skaf, Alain Guyot:
Design of a GaAs redundant divider. VLSI 1993: 63-72 - Poul Martin Rands Jensen:
An ASIC array architecture for the DITPOS algorithm. VLSI 1993: 73-82 - J. Morris Chang, Edward F. Gehringer:
Performance of object caching for object-oriented systems. VLSI 1993: 83-91 - Ali Skaf, Jean-Claude Bajard, Alain Guyot, Jean-Michel Muller:
A VLSI circuit for on-line polynominal computing: Application to exponential, trigonometric and hyperbolic functions. VLSI 1993: 93-100
Design for Testability
- Michael Gössel, Egor S. Sogomonyan:
Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design. VLSI 1993: 103-111 - Albrecht P. Stroele:
Partitioning and hierarchical description of self-testable designs. VLSI 1993: 113-122 - Régis Leveugle:
Test of single fault tolerant controllers in VLSI circuits. VLSI 1993: 123-132 - W. A. J. Waller, S. M. Aziz:
A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. VLSI 1993: 133-142
Image Processing
- D. Poussart:
Opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensors. VLSI 1993: 145-150 - Jörg Schönfeld, Peter Pirsch:
Single board image processing unit for vehicle guidance. VLSI 1993: 151-160 - Jaap Smit, Mark J. Bentum, Martin M. Samsom:
Implementation of the volume rendering algorithm using a low-power design-style. VLSI 1993: 161-168 - D. Jacquet, Gabriele Saucier:
Design of a dedicated neural network on silicon: application to optical character recognition. VLSI 1993: 169-178
High Performance Processors
- Mike Muller:
ARM6: Processor design for high performance at low power. VLSI 1993: 181-189 - Albert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens:
A new method for retiming multi-functional processing units. VLSI 1993: 191-200 - Ganesh Gopalakrishnan, Venkatesh Akella:
A transformational approach to asynchronous high-level synthesis. VLSI 1993: 201-210 - Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods:
A micropipelined ARM. VLSI 1993: 211-220 - F. Poirier, Jean-Claude Heudin, M. Belleville, C. Jaffard:
A high performance RISC microprocessor. VLSI 1993: 221-228
Low Level Models
- Wolfgang Röthig, Elmar U. K. Melcher, Michel Dana:
Probabilistic power consumption estimation in digital circuits. VLSI 1993: 231-240 - Maximilian Erbar, Ingo Könenkamp, Ernst-Helmut Horneber:
Solving the partial differential equations of transmission lines with wave digital filters. VLSI 1993: 241-250 - M. Schneider, Utz Wever, Qinghua Zheng:
Parallel harmonic balance. VLSI 1993: 251-260 - Norbert Wehn, Manfred Glesner, C. Vielhauer:
Estimating lower hardware bounds in high-level synthesis. VLSI 1993: 261-270
Multichip Modules
- Christer Svensson, Jiren Yuan:
Ultra high speed CMOS design. VLSI 1993: 273-282 - Claus M. Habiger, Ian P. Jalowiecki:
The implementation of a MCM associative string processor. VLSI 1993: 283-289 - Bertrand Cabon, T. V. Dinh, J. Chilo:
Superconductive interconnections in multi-chip modules. VLSI 1993: 291-298
Routing
- Mikiko Sode Tanaka, Masaki Ishikawa:
A multilayer channel router based on optimal multilayer net assignment. VLSI 1993: 301-310 - Kevin Bolding, Sen-Ching S. Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille:
The chaos router chip: design and implementation of an adaptive router. VLSI 1993: 311-320 - Tianxiong Xue, Takashi Fujii, Ernest S. Kuh:
A new performance-driven global routing algorithm for gate array. VLSI 1993: 321-330
Simulation
- Shen Lin, Ernest S. Kuh:
Circuit simulation for large interconnected IC networks. VLSI 1993: 333-342 - Markus Müller:
Bondgraph execution as a new algorithm for circuit simulation. VLSI 1993: 343-352 - Avinash C. Palaniswamy, Philip A. Wilsey:
Adaptive checkpoint intervals in an optimistically synchronised parallel digital system simulator. VLSI 1993: 353-362
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