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ORCID31st SoCC 2018: Arlington, VA, USA
- 31st IEEE International System-on-Chip Conference, SOCC 2018, Arlington, VA, USA, September 4-7, 2018. IEEE 2018, ISBN 978-1-5386-1491-4
- Yiming Zhao, Xiaohang Wang, Yingtao Jiang, Mei Yang, Amit Kumar Singh, Terrence S. T. Mak:
On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems. 1-6 - Hugo Daniel Hernández
, Lucas C. Severo, Wilhelmus A. M. Van Noije:
0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS Technology. 1-4 - Hemanta Kumar Mondal, Rodrigo Cadore Cataldo, César Augusto Missio Marcon, Kevin J. M. Martin, Sujay Deb, Jean-Philippe Diguet:
Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing. 1-6 - Yasin Bastan, Ali Nejati, Sara Radfar, Parviz Amiri, Mehdi Nasrollahpour, Sotoudeh Hamedi-Hagh:
An Ultra-Low-Voltage Sub-Threshold Pseudo-Differential CMOS Schmitt Trigger. 1-5 - Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin:
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. 1-6 - Josiah D. Hester, Tianyu Jia, Jie Gu:
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. 7-12 - Michael Adelbert Gacusan, V. Muthukumar:
Cloud Motion Vector Estimation Using Scalable Wireless Sensor Networks. 13-18 - Sanad Kawar, Shoba Krishnan, Khaldoon Abugharbieh:
A Discontinuous Charging Technique with Programmable Duty-Cycle for Switched-Capacitor Based Energy Harvesting Circuits in IoT Applications. 19-22 - Siamak Delshadpour, Ahmad Yazdi, Michael Geng, Xu Zhang, Abhijeet Kulkarni, Ken Jaramillo:
An FSK Transceiver for USB Power Delivery in 0.14-μm CMOS Technology. 23-28 - Siamak Delshadpour:
A 64 dB Dynamic Range Programmable Gain Amplifier for Dual Band WLAN 802.11abg IF Receiver in 0.18 μm CMOS Technology. 29-32 - Mehdi Nasrollahpour, Amir Mahdavi, Sotoudeh Hamedi-Hagh:
Design and Analysis of 66GHz Voltage Controlled Oscillators for FMCW Radar Applications with Phase Noise Impact Consideration. 33-36 - Md Musabbir Adnan, Sagarvarma Sayyaparaju, Garrett S. Rose, Catherine D. Schuman, Bon Woong Ku, Sung Kyu Lim:
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems. 37-42 - Jiawei Xu, Yuxiang Huan, Li-Rong Zheng, Zhuo Zou:
A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks. 43-48 - Arnab A. Purkayastha, Suhas Ashok Shiddhibhavi, Hamed Tabkhi:
Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications. 55-60 - Kaiyou Li, Haoxin Zheng, Bing Mo, Jianping Guo, Dihu Chen:
A New Circuit Topology for High-Performance Pulsed Time-of- Flight Laser Radar Receivers. 78-83 - Matthew Hagan, Fahad Siddiqui, Sakir Sezer:
Policy-Based Security Modelling and Enforcement Approach for Emerging Embedded Architectures. 84-89 - Qian Wang, Zhaojun Lu, Gang Qu:
An Entropy Analysis Based Intrusion Detection System for Controller Area Network in Vehicles. 90-95 - Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Abhijit Karmakar, Raj Singh:
A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs. 96-101 - Weize Yu, Yiming Wen:
Leakage Power Analysis (LPA) Attack in Breakdown Mode and Countermeasure. 102-105 - S. Navid Shahrouzi, Darshika G. Perera:
Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs. 106-111 - Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera:
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. 112-117 - Haoming Chu, Yuxiang Huan, Dongxuan Bao, Bengt Källbäck, Yajie Qin, Zhuo Zou, Lirong Zheng:
An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed Sampling. 124-129 - Changqing Xu, Yi Liu, Yintang Yang:
A Multi-Objective Architecture Optimization Method for Application-Specific Noc Design. 130-135 - Shrikant S. Jadhav, Noah LaMoyne, Alan Chen, Clay Gloster, Dylan Yang, Sunmin Yun, Youngsoo Kim:
Building an Acceleration Overlay for Novice Students. 136-139 - Fahad Siddiqui, Matthew Hagan, Sakir Sezer:
Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCs. 140-145 - Nishtha Sharma, C. Binek, Andrew Marshall, Jonathan P. Bird, Peter A. Dowben, Dmitri E. Nikonov:
Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits. 146-151 - Kasem Khalil, Omar Eldash, Ashok Kumar, Magdy A. Bayoumi:
Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture. 152-157 - Mattia Cacciotti, Vincent Camus, Jeremy Schlachter, Alessandro Pezzotta, Christian C. Enz:
Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis. 158-162 - Amin Norollah, Danesh Derafshi, Hakem Beitollahi, Ahmad Patooghy:
PAT-Noxim: A Precise Power & Thermal Cycle-Accurate NoC Simulator. 163-168 - Armin Mehrabian, Yousra Al-Kabani, Volker J. Sorger, Tarek A. El-Ghazawi:
PCNNA: A Photonic Convolutional Neural Network Accelerator. 169-173 - Steffen Baehr, Fabian Kempf, Jürgen Becker:
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks. 174-179 - Lafifa Jamal, Md. Riaz Uddin:
Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits. 180-185 - Peter A. Zientara, Jack Sampson, Vijaykrishnan Narayanan:
Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms. 186-191 - Chuang-An Mao, Yu Xie, Yizhuang Xie, He Chen, Hao Shi:
An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGA. 192-196 - Shivakumar Chonnad, Radu Iacob, Vladimir Litovtchenko:
A Quantitative Approach to SoC Functional Safety Analysis. 197-202 - Ankush Mamgain, Anuj Grover:
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology. 203-208 - Shun-Wen Cheng, Chun-Pin Lin, Chi-Shi Chen, Wei-Chang Tsai:
Universal CMOS Diamond-Graph Circuit for Embedded Computing. 206-212 - Keyvan Ramezanpour, Paul Ampadu:
Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching. 206-212 - Tanja Harbaum, Matthias Norbert Balzer, Marc Weber, Jürgen Becker:
A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique. 206-212 - Siji Huang, Yicheng Li, Bing Mo, Jianping Guo, Dihu Chen:
An Output-Capacitorless Adaptively Biased Low-Dropout Regulator with Maximum 132-MHz UGF and Without Minimum Loading Requirement. 206-212 - Naveed Mahmud, Esam El-Araby:
A Scalable High-Precision and High-Throughput Architecture for Emulation of Quantum Algorithms. 206-212 - Mesbah Uddin, Garrett S. Rose:
A Practical Sense Amplifier Design for Memristive Crossbar Circuits (PUF). 209-214 - Jungho Kim, Philkyue Shin, Soonhyun Noh, Daesik Ham, Seongsoo Hong:
Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux Cgroup. 215-220 - Byungmin Ahn, Taewhan Kim:
Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks. 221-226 - Huaipan Jiang, Anup Sarma, Jihyun Ryoo, Jagadish B. Kotra, Meena Arunachalam, Chita R. Das, Mahmut T. Kandemir:
A Learning-Guided Hierarchical Approach for Biomedical Image Segmentation. 227-232 - Jun Hyuk Park, Soobum Kwon, Kyusun Choi:
Designing Algorithm for the High Speed TIQ ADC, with Improved Accuracy. 233-237 - Morteza Hosseini, Rashidul Islam, Lahir Marni, Tinoosh Mohsenin:
MPT: Multiple Parallel Tempering for High-Throughput MCMC Samplers. 244-249 - Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang:
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. 250-253 - Alec Roelke, Mircea R. Stan:
Co-Optimizing CPUs and Accelerators in Constrained Systems. 254-259 - Md Farhadur Reza, Dan Zhao, Magdy A. Bayoumi:
Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era. 260-265 - Samira Ataei, James E. Stine:
A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. 266-271 - Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. 272-277 - Han Xu, Fei Qiao, Zhe Chen, Qi Wei, Xinjun Liu, Huazhong Yang:
Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN Processors. 278-283 - M. Meraj Ahmed, Amlan Ganguly, Sajeed Mohaamd Shahriat, Hardeep Pruswani, Naseef Mansoor:
A One-to-Many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing Platforms. 284-289 - Pengzhan Yan, Ramalingam Sridhar:
Centralized Priority Management Allocation for Network-on-Chip Router. 290-295 - Mathieu Coustans, François Krummenacher, Maher Kayal, Lucas Rossi, Mario Dellea, Yves Godat, Yves Sierro, Silvio DallaPiazza:
A 32kHz Crystal Oscillator Leveraging Voltage Scaling in an Ultra-Low Power 40NA Real-Time Clock. 308-313 - Mihir Mody, Kedar Chitnis, Piyali Goswami, Brijesh Jadav, Shiju Sivasankaran, Gregory Shurtz, Rajat Sagar, Abhinay Armstrong, Shashank Dabral, Prasad Jondhale, Yashwant Dutt, Jason Jones:
Integrated Surround & CMS Automotive SoC. 318-321 - Motoi Ichihashi, Youngtag Woo, Muhammed Ahosan Ul Karim, Vivek Joshi, David Burnett:
10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application. 322-325 - Siamak Delshadpour, Ahmad Yazdi, Soon-Gil Jung, Xu Zhang, Michael Geng, Leo Liu, Ranjeet Kumar Gupta:
Low Power 20.625 Gbps Type-C USB3.2/DPl.4/ Thunderbolt3 Combo Linear Redriver in 0.25 μm BiCMOS Technology. 326-329
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