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S. Navid Shahrouzi
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2020 – today
- 2024
- [j4]Mokhles A. Mohsin
, S. Navid Shahrouzi
, Darshika G. Perera
:
Composing Efficient Computational Models for Real-Time Processing on Next-Generation Edge-Computing Platforms. IEEE Access 12: 24905-24932 (2024) - 2020
- [j3]S. Navid Shahrouzi, Arkan Alkamil, Darshika G. Perera
:
Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs. IEEE Access 8: 91531-91545 (2020)
2010 – 2019
- 2019
- [j2]S. Navid Shahrouzi
, Darshika G. Perera
:
Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis. Microprocess. Microsystems 65: 79-96 (2019) - [c4]S. Navid Shahrouzi, Darshika G. Perera:
HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools. PACRIM 2019: 1-9 - 2018
- [c3]S. Navid Shahrouzi, Darshika G. Perera:
Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs. SoCC 2018: 106-111 - 2017
- [j1]S. Navid Shahrouzi, Darshika G. Perera
:
Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices. EURASIP J. Embed. Syst. 2017: 25 (2017) - [c2]S. Navid Shahrouzi, Darshika G. Perera:
An efficient embedded multi-ported memory architecture for next-generation FPGAs. ASAP 2017: 83-90 - [c1]S. Navid Shahrouzi, Darshika G. Perera:
An efficient FPGA-based memory architecture for compute-intensive applications on embedded devices. PACRIM 2017: 1-8
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last updated on 2024-04-25 01:23 CEST by the dblp team
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