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"A Highly Parallel FPGA Implementation of Sparse Neural Network Training."

Sourya Dey et al. (2018)

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DOI: 10.1109/RECONFIG.2018.8641739

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-25

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  dblp key:
  - conf/reconfig/DeyCLKHCB18
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  - https://dblp.org/rec/conf/reconfig/DeyCLKHCB18
Sourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel:
A Highly Parallel FPGA Implementation of Sparse Neural Network Training. ReConFig 2018: 1-4

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