Stop the war!
Остановите войну!
for scientists:
default search action
Search dblp for Publications
export results for "toc:db/conf/fpl/fpl2000.bht:"
@inproceedings{DBLP:conf/fpl/AbkeB00, author = {Joerg Abke and Erich Barke}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {191--200}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_22}, doi = {10.1007/3-540-44614-1\_22}, timestamp = {Tue, 14 May 2019 10:00:48 +0200}, biburl = {https://dblp.org/rec/conf/fpl/AbkeB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/AmanoSU00, author = {Hideharu Amano and Yuichiro Shibata and Masaki Uno}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Reconfigurable Systems: New Activities in Asia}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {585--594}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_63}, doi = {10.1007/3-540-44614-1\_63}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/AmanoSU00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/AndersonSNMJ00, author = {Jason Helge Anderson and Jim Saunders and Sudip Nag and Chari Madabhushi and Rajeev Jayaraman}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Placement Algorithm for {FPGA} Designs with Multiple {I/O} Standards}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {211--220}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_24}, doi = {10.1007/3-540-44614-1\_24}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/AndersonSNMJ00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/AndrejasT00, author = {Jernej Andrejas and Andrej Trost}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Reusable {DSP} Functions in FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {456--461}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_49}, doi = {10.1007/3-540-44614-1\_49}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/AndrejasT00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/AoyamaSNN00, author = {Kazuo Aoyama and Hiroshi Sawada and Akira Nagoya and Kazuo Nakajima}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {665--674}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_71}, doi = {10.1007/3-540-44614-1\_71}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/AoyamaSNN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BartzickHKW00, author = {Thomas Bartzick and Michael Henze and Jens Kickler and Kai Woska}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Design of a Fault Tolerant {FPGA}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {151--156}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_16}, doi = {10.1007/3-540-44614-1\_16}, timestamp = {Wed, 26 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BartzickHKW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BauerZW00, author = {Christine Bauer and Peter Zipf and Hans Wojtkowiak}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {System Design with Genetic Algorithms}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {250--259}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_28}, doi = {10.1007/3-540-44614-1\_28}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BauerZW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BeckerPG00, author = {J{\"{u}}rgen Becker and Thilo Pionteck and Manfred Glesner}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {DReAM: {A} Dynamically Reconfigurable Architecture for Future Mobile Communications Applications}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {312--321}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_34}, doi = {10.1007/3-540-44614-1\_34}, timestamp = {Fri, 19 Jul 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BeckerPG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BellisM00, author = {Stephen J. Bellis and William P. Marnane}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A {CORDIC} Arctangent {FPGA} Implementation for a High-Speed 3D-Camera System}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {485--494}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_53}, doi = {10.1007/3-540-44614-1\_53}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BellisM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BlaicknerNG00, author = {Alfred Blaickner and O. Nagy and Herbert Gr{\"{u}}nbacher}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {322--331}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_35}, doi = {10.1007/3-540-44614-1\_35}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BlaicknerNG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Blodget00, author = {Brandon Blodget}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Pre-route Assistant: {A} Routing Tool for Run-Time Reconfiguration}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {797--800}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_88}, doi = {10.1007/3-540-44614-1\_88}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Blodget00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BobdaL00, author = {Christophe Bobda and Thomas Lehmann}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {759--768}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_80}, doi = {10.1007/3-540-44614-1\_80}, timestamp = {Fri, 27 Jul 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BobdaL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BrinkmannLR00, author = {Andr{\'{e}} Brinkmann and Dominik Langen and Ulrich R{\"{u}}ckert}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {838--841}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_98}, doi = {10.1007/3-540-44614-1\_98}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BrinkmannLR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/CantoMCLI00, author = {E. Cant{\'{o}} and Juan Manuel Moreno and Joan Cabestany and Ignacio Lacadena and Josep Maria Insenser}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Implementation of Virtual Circuits by Means of the {FIPSOC} Devices}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {87--95}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_10}, doi = {10.1007/3-540-44614-1\_10}, timestamp = {Mon, 01 Feb 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/CantoMCLI00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/CaspiCHYWD00, author = {Eylon Caspi and Michael Chu and Randy Huang and Joseph Yeh and John Wawrzynek and Andr{\'{e}} DeHon}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Stream Computations Organized for Reconfigurable Execution {(SCORE)}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {605--614}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_65}, doi = {10.1007/3-540-44614-1\_65}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/CaspiCHYWD00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ChengWH00, author = {Winnie W. Cheng and Steven J. E. Wilton and Babak Hamidzadeh}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {{FPGA} Implementation of a Prototype {WDM} On-Line Scheduler}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {773--776}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_82}, doi = {10.1007/3-540-44614-1\_82}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ChengWH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ConstantinidesCL00, author = {George A. Constantinides and Peter Y. K. Cheung and Wayne Luk}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Multiple-Wordlength Resource Binding}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {646--655}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_69}, doi = {10.1007/3-540-44614-1\_69}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ConstantinidesCL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/CourtneyTW00, author = {Tim Courtney and Richard H. Turner and Roger F. Woods}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Multiplexer Based Reconfiguration for Virtex Multipliers}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {749--758}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_79}, doi = {10.1007/3-540-44614-1\_79}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/CourtneyTW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/DerbyshireL00, author = {Arran Derbyshire and Wayne Luk}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Combining Serialisation and Reconfiguration for {FPGA} Designs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {636--645}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_68}, doi = {10.1007/3-540-44614-1\_68}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/DerbyshireL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/DiesselM00, author = {Oliver Diessel and George J. Milne}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Behavioural Language Compilation with Virtual Hardware Management}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {707--717}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_75}, doi = {10.1007/3-540-44614-1\_75}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/DiesselM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/DitmarTJ00, author = {Johan Ditmar and Kjell Torkelsson and Axel Jantsch}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {19--28}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_3}, doi = {10.1007/3-540-44614-1\_3}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/DitmarTJ00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/DoringL00, author = {Andreas C. D{\"{o}}ring and Gunther Lustig}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Generating Addresses for Multi-dimensional Array Access in {FPGA} On-chip Memory}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {626--635}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_67}, doi = {10.1007/3-540-44614-1\_67}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/DoringL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/EdwardsG00, author = {Martyn Edwards and Peter Green}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {739--748}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_78}, doi = {10.1007/3-540-44614-1\_78}, timestamp = {Tue, 17 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/EdwardsG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/EisenringP00, author = {Michael Eisenring and Marco Platzner}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Optimization of Run-Time Reconfigurable Embedded Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {565--574}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_61}, doi = {10.1007/3-540-44614-1\_61}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/EisenringP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ElGindyMSS00, author = {Hossam A. ElGindy and Martin Middendorf and Hartmut Schmeck and Bernd Schmidt}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {379--388}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_41}, doi = {10.1007/3-540-44614-1\_41}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ElGindyMSS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/EmmertSCTKA00, author = {John Marty Emmert and Charles E. Stroud and Jason A. Cheatham and Andrew M. Taylor and Pankaj Kataria and Miron Abramovici}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Performance Penalty for Fault Tolerance in Roving STARs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {545--554}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_59}, doi = {10.1007/3-540-44614-1\_59}, timestamp = {Thu, 27 Apr 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/EmmertSCTKA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/EnzlerJCT00, author = {Rolf Enzler and Tobias Jeger and Didier Cottet and Gerhard Tr{\"{o}}ster}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {525--534}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_57}, doi = {10.1007/3-540-44614-1\_57}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/EnzlerJCT00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/FabianiL00, author = {Erwan Fabiani and Dominique Lavenier}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Placement of Linear Arrays}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {849--852}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_101}, doi = {10.1007/3-540-44614-1\_101}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/FabianiL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/FallsideS00, author = {Hamish Fallside and Michael John Sebastian Smith}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Internet Connected {FPL}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {48--57}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_6}, doi = {10.1007/3-540-44614-1\_6}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/FallsideS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/GauseCL00, author = {J{\"{o}}rn Gause and Peter Y. K. Cheung and Wayne Luk}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive {DCT}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {96--105}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_11}, doi = {10.1007/3-540-44614-1\_11}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/GauseCL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/GironesHSS00, author = {Rafael Gadea Giron{\'{e}}s and Vicente Herrero{-}Bosch and Angel Sebasti{\'{a}} and Antonio Mochol{\'{\i}} Salcedo}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {The Role of the Embedded Memories in the Implementation of Artificial Neural Networks}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {785--788}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_85}, doi = {10.1007/3-540-44614-1\_85}, timestamp = {Sat, 11 Feb 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/GironesHSS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/GlasmacherW00, author = {Alexander Glasmacher and Kai Woska}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Design and Implementation of an {XC6216} {FPGA} Model in Verilog}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {449--455}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_48}, doi = {10.1007/3-540-44614-1\_48}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/GlasmacherW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/GovindarajanV00, author = {Sriram Govindarajan and Ranga Vemuri}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in {SPARCS}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {7--18}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_2}, doi = {10.1007/3-540-44614-1\_2}, timestamp = {Sat, 09 Apr 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/GovindarajanV00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/GroverSL00, author = {Radhika S. Grover and Weijia Shang and Qiang Li}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Comparison of {FPGA} Implementations of Bit-Level and Word-Level Matrix Multipliers}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {422--431}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_45}, doi = {10.1007/3-540-44614-1\_45}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/GroverSL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/HartensteinHHN00, author = {Reiner W. Hartenstein and Michael Herz and Thomas Hoffmann and Ulrich Nageldinger}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {389--399}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_42}, doi = {10.1007/3-540-44614-1\_42}, timestamp = {Tue, 08 Dec 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/HartensteinHHN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/HatnikHS00, author = {Uwe Hatnik and J{\"{u}}rgen Haufe and Peter Schwarz}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {An Innovative Approach to Couple {EDA} Tools with Reconfigurable Hardware}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {826--829}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_95}, doi = {10.1007/3-540-44614-1\_95}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/HatnikHS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/HeystersSSH00, author = {Paul M. Heysters and Jaap Smit and Gerard J. M. Smit and Paul J. M. Havinga}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Mapping of {DSP} Algorithms on Field Programmable Function Arrays}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {400--411}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_43}, doi = {10.1007/3-540-44614-1\_43}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/HeystersSSH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/HildebrandtT00, author = {Jens Hildebrandt and Dirk Timmermann}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {An {FPFA} Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {777--780}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_83}, doi = {10.1007/3-540-44614-1\_83}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/HildebrandtT00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/HiltonH00, author = {A. Hilton and J. Hall}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {On Applying Software Development Best Practice to FPFAs in Safety Critical Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {793--796}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_87}, doi = {10.1007/3-540-44614-1\_87}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/HiltonH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/HoffmannUVW00, author = {Rolf Hoffmann and Bernd Ulmann and Klaus{-}Peter V{\"{o}}lkmann and Stefan Waldschmidt}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Stream Processor Architecture Based on the Configurable {CEPRA-S}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {822--825}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_94}, doi = {10.1007/3-540-44614-1\_94}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/HoffmannUVW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/IchikawaSUK00, author = {Shuichi Ichikawa and Hidemitsu Saito and Lerdtanaseangtham Udorn and Kouji Konishi}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Evaluation of Accelerator Designs for Subgraph Isomorphism Problem}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {729--738}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_77}, doi = {10.1007/3-540-44614-1\_77}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/IchikawaSUK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/IliopoulosA00, author = {Marios Iliopoulos and Theodore Antonakopoulos}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {39--47}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_5}, doi = {10.1007/3-540-44614-1\_5}, timestamp = {Thu, 23 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/IliopoulosA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/JainKK00, author = {Sushil Chandra Jain and Anshul Kumar and Shashi Kumar}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {201--210}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_23}, doi = {10.1007/3-540-44614-1\_23}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/JainKK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KastrupTMHM00, author = {Bernardo Kastrup and Jeroen Trum and Orlando Moreira and Jan Hoogerbrugge and Jef L. van Meerbergen}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Compiling Applications for ConCISe: An Example of Automatic {HW/SW} Partitioning and Synthesis}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {695--706}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_74}, doi = {10.1007/3-540-44614-1\_74}, timestamp = {Sat, 16 Sep 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KastrupTMHM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Kean00, author = {Tom Kean}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {575--584}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_62}, doi = {10.1007/3-540-44614-1\_62}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Kean00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KoboriMH00, author = {Tomoyoshi Kobori and Tsutomu Maruyama and Tsutomu Hoshino}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {High Speed Computation of Lattice gas Automata with {FPFA}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {801--804}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_89}, doi = {10.1007/3-540-44614-1\_89}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KoboriMH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Krasniewski00, author = {Andrzej Krasniewski}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {675--684}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_72}, doi = {10.1007/3-540-44614-1\_72}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Krasniewski00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KressPS00, author = {Rainer Kress and Andreas Pyttel and Alexander Sedlmeier}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {FPGA-Based Prototyping for Product Definition}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {78--86}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_9}, doi = {10.1007/3-540-44614-1\_9}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KressPS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KrishnamoorthyST00, author = {Srini Krishnamoorthy and Sriram Swaminathan and Russell Tessier}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Area-Optimized Technology Mapping for Hybrid FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {181--190}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_21}, doi = {10.1007/3-540-44614-1\_21}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KrishnamoorthyST00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KroppR00, author = {Holger Kropp and Carsten Reuter}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Mapping Methodology for Code Trees onto LUT-Based FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {221--229}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_25}, doi = {10.1007/3-540-44614-1\_25}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KroppR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KrupnovaS00, author = {Helena Krupnova and Gabriele Saucier}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {FPGA-Based Emulation: Industrial and Custom Prototyping Solutions}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {68--77}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_8}, doi = {10.1007/3-540-44614-1\_8}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KrupnovaS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Lafayette00, author = {Guy Lecurieux Lafayette}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Programmable System Level Integration Brings System-on-Chip Design to the Desktop}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {789--792}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_86}, doi = {10.1007/3-540-44614-1\_86}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Lafayette00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LangeK00, author = {Holger Lange and Andreas Koch}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Memory Access Schemes for Configurable Processors}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {615--625}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_66}, doi = {10.1007/3-540-44614-1\_66}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/LangeK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LiasVDM00, author = {G. L{\'{\i}}as and Mar{\'{\i}}a Dolores Vald{\'{e}}s and Miguel A. Dom{\'{\i}}nguez and Mar{\'{\i}}a Jos{\'{e}} Moure}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Implementing a Fieldbus Interface Using an {FPGA}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {175--180}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_20}, doi = {10.1007/3-540-44614-1\_20}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/LiasVDM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Makimoto00, author = {Tsugio Makimoto}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {The Rising Wave of Field Programmability}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {1--6}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_1}, doi = {10.1007/3-540-44614-1\_1}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Makimoto00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MatasaruJ00, author = {Bogdan Matasaru and Tudor Jebelean}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {{FPGA} Implementation of an Extended Binary {GCD} Algorithm for Systolic Reduction of Rational Numbers}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {810--813}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_91}, doi = {10.1007/3-540-44614-1\_91}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/MatasaruJ00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MayaRTA00, author = {Selene Maya and M. Rocio Reynoso and C{\'{e}}sar Torres{-}Huitzil and Miguel O. Arias{-}Estrada}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Compact Spiking Neural Network Implementation in {FPGA}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {270--276}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_30}, doi = {10.1007/3-540-44614-1\_30}, timestamp = {Fri, 08 Jan 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/MayaRTA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/McCaskillW00, author = {John S. McCaskill and Patrick Wagler}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {286--299}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_32}, doi = {10.1007/3-540-44614-1\_32}, timestamp = {Thu, 15 Jun 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/McCaskillW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/McCready00, author = {Rob McCready}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Real-Time Face Detection on a Configurable Hardware System}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {157--162}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_17}, doi = {10.1007/3-540-44614-1\_17}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/McCready00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/McMillanG00, author = {Scott McMillan and Steve Guccione}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Partial Run-Time Reconfiguration Using {JRTR}}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {352--360}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_38}, doi = {10.1007/3-540-44614-1\_38}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/McMillanG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MelnikoffJQR00, author = {Stephen J. Melnikoff and Philip James{-}Roxby and Steven F. Quigley and Martin J. Russell}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Reconfigurable Computing for Speech Recognition: Preliminary Findings}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {495--504}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_54}, doi = {10.1007/3-540-44614-1\_54}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/MelnikoffJQR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MencerHMF00, author = {Oskar Mencer and Heiko H{\"{u}}bert and Martin Morf and Michael J. Flynn}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {595--604}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_64}, doi = {10.1007/3-540-44614-1\_64}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/MencerHMF00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MiomoYK00, author = {Takahiro Miomo and Koichi Yasuoka and Masanori Kanazawa}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {The Fastest Multiplier on FPGAs with Redundant Binary Representation}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {515--524}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_56}, doi = {10.1007/3-540-44614-1\_56}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/MiomoYK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/NogueraB00, author = {Juanjo Noguera and Rosa M. Badia}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {842--845}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_99}, doi = {10.1007/3-540-44614-1\_99}, timestamp = {Thu, 15 Jun 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/NogueraB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Pfeifer00, author = {Petr Pfeifer}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Multifunctional Programmable Single-Board {CAN} Monitoring Module}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {163--168}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_18}, doi = {10.1007/3-540-44614-1\_18}, timestamp = {Fri, 02 Jun 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Pfeifer00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Phillips00, author = {Chris Phillips}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Wireless Base Station Design Using a Reconfigurable Communications Processor}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {846--848}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_100}, doi = {10.1007/3-540-44614-1\_100}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Phillips00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/PloogST00, author = {Hagen Ploog and Mathias Schmalisch and Dirk Timmermann}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Security Upgrade of Existing {ISDN} Devices by Using Reconfigurable Logic}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {505--514}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_55}, doi = {10.1007/3-540-44614-1\_55}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/PloogST00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/QiaoIA00, author = {Jian Qiao and Makoto Ikeda and Kunihiro Asada}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Optimum Functional Decomposition for LUT-Based {FPGA} Synthesis}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {555--564}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_60}, doi = {10.1007/3-540-44614-1\_60}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/QiaoIA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Rabaey00, author = {Jan M. Rabaey}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {277--285}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_31}, doi = {10.1007/3-540-44614-1\_31}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Rabaey00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RaczinskiS00, author = {Jean{-}Michel Raczinski and St{\'{e}}phane Sladek}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {The Modular Architecture of SYNTHUP, {FPFA} Based {PCI} Board for Real-Time Sound Synthesis and Digital Signal Processing}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {834--837}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_97}, doi = {10.1007/3-540-44614-1\_97}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/RaczinskiS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RamirezGFPL00, author = {Javier Ram{\'{\i}}rez and Antonio Garc{\'{\i}}a and Pedro G. Fern{\'{a}}ndez and Luis Parrilla and Antonio Lloris{-}Ru{\'{\i}}z}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Analysis of {RNS-FPL} Synergy for High Throughput {DSP} Applications: Discrete Wavelet Transform}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {342--351}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_37}, doi = {10.1007/3-540-44614-1\_37}, timestamp = {Fri, 13 Nov 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/RamirezGFPL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RedekoppD00, author = {Mark Redekopp and Andreas Dandalis}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Parallel Pipelined {SAT} Solver for FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {462--468}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_50}, doi = {10.1007/3-540-44614-1\_50}, timestamp = {Wed, 10 Nov 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/RedekoppD00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RennerBG00, author = {Frank{-}Michael Renner and J{\"{u}}rgen Becker and Manfred Glesner}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Field Programmable Communication Emulation and Optimization for Embedded System Design}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {58--67}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_7}, doi = {10.1007/3-540-44614-1\_7}, timestamp = {Fri, 19 Jul 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/RennerBG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Renovell00, author = {Michel Renovell}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Specific Test Methodology for Symmetric SRAM-Based FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {300--311}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_33}, doi = {10.1007/3-540-44614-1\_33}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Renovell00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RevesGCG00, author = {Xavier Rev{\'{e}}s and Antoni Gelonch and Ferran Casadevall and Jos{\'{e}} L. Garc{\'{\i}}a}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Software Radio Reconfigurable Hardware System (SHaRe)}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {332--341}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_36}, doi = {10.1007/3-540-44614-1\_36}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/RevesGCG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RissaN00, author = {Tero Rissa and Jarkko Niittylahti}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {371--378}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_40}, doi = {10.1007/3-540-44614-1\_40}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/RissaN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RobinsonL00, author = {David Robinson and Patrick Lysaght}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Verification of Dynamically Reconfigurable Logic}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {141--150}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_15}, doi = {10.1007/3-540-44614-1\_15}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/RobinsonL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SawitykiSSS00, author = {Sergej Sawitzki and Jens Sch{\"{o}}nherr and Rainer G. Spallek and Bernd Straube}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Formal Verification of a Reconfigurable Microprocessor}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {781--784}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_84}, doi = {10.1007/3-540-44614-1\_84}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SawitykiSSS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SekaninaS00, author = {Luk{\'{a}}s Sekanina and Azeddien M. Sllame}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Toward Uniform Approach to Design of Evolvable Hardware Based Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {814--817}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_92}, doi = {10.1007/3-540-44614-1\_92}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SekaninaS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ShiozawaINONN00, author = {Tsunemichi Shiozawa and Norbert Imlig and Kouichi Nagami and Kiyoshi Oguri and Akira Nagoya and Hiroshi Nakada}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {An Implementation of Longest Prefix Matching for {IP} Router on Plastic Cell Architecture}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {805--809}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_90}, doi = {10.1007/3-540-44614-1\_90}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ShiozawaINONN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SidhuWMP00, author = {Reetinder P. S. Sidhu and Sameer Wadhwa and Alessandro Mei and Viktor K. Prasanna}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Self-Reconfigurable Gate Array Architecture}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {106--120}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_12}, doi = {10.1007/3-540-44614-1\_12}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SidhuWMP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Siemers00, author = {Christian Siemers}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {769--772}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_81}, doi = {10.1007/3-540-44614-1\_81}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Siemers00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SimmlerLM00, author = {Harald Simmler and L. Levinson and Reinhard M{\"{a}}nner}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Multitasking on {FPGA} Coprocessors}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {121--130}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_13}, doi = {10.1007/3-540-44614-1\_13}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SimmlerLM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Skylarov00, author = {Valery Sklyarov}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {718--728}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_76}, doi = {10.1007/3-540-44614-1\_76}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Skylarov00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/StefanovicM00, author = {Darko Stefanovic and Margaret Martonosi}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {On Availability of Bit-Narrow Operations in General-Purpose Applications}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {412--421}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_44}, doi = {10.1007/3-540-44614-1\_44}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/StefanovicM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/TakayamaSIA00, author = {Atsushi Takayama and Yuichiro Shibata and Keisuke Iwai and Hideharu Amano}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {685--694}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_73}, doi = {10.1007/3-540-44614-1\_73}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/TakayamaSIA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/TammemaeE00, author = {Kalle Tammem{\"{a}}e and T. Evartson}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {{FPL} Curriculum at Tallinn Technical University}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {830--833}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_96}, doi = {10.1007/3-540-44614-1\_96}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/TammemaeE00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/TangAJ00, author = {Xinan Tang and Manning Aalsma and Raymond Jou}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {29--38}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_4}, doi = {10.1007/3-540-44614-1\_4}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/TangAJ00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/TessierG00, author = {Russell Tessier and Heather Giza}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Balancing Logic Utilization and Area Efficiency in FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {535--544}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_58}, doi = {10.1007/3-540-44614-1\_58}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/TessierG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Tomaszewicz00, author = {Pawel Tomaszewicz}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Self-Testing of Linear Segments in User-Programmed FPGAs}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {169--174}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_19}, doi = {10.1007/3-540-44614-1\_19}, timestamp = {Sat, 19 Oct 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Tomaszewicz00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Torresen00, author = {Jim T{\o}rresen}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {230--239}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_26}, doi = {10.1007/3-540-44614-1\_26}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Torresen00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Touhafi00, author = {Abdellah Touhafi}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {469--474}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_51}, doi = {10.1007/3-540-44614-1\_51}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Touhafi00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/TrostZZ00, author = {Andrej Trost and Andrej Zemva and Baldomir Zajc}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Educational Programmable Hardware Prototyping and Verification System}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {818--821}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_93}, doi = {10.1007/3-540-44614-1\_93}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/TrostZZ00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/Vasilko00, author = {Milan Vasilko}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Design Visualisation for Dynamically Reconfigurable Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {131--140}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_14}, doi = {10.1007/3-540-44614-1\_14}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/Vasilko00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/VasilkoB00, author = {Milan Vasilko and Graham Benyon{-}Tinker}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Automatic Temporal Floorplanning with Guaranteed Solution Feasibility}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {656--664}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_70}, doi = {10.1007/3-540-44614-1\_70}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/VasilkoB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/WadhwaD00, author = {Sameer Wadhwa and Andreas Dandalis}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Efficient Self-Reconfigurable Implementations Using On-chip Memory}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {443--448}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_47}, doi = {10.1007/3-540-44614-1\_47}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/WadhwaD00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/WolzK00, author = {Frank Wolz and Reiner Kolla}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A New Floorplanning Method for {FPGA} Architectural Research}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {432--442}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_46}, doi = {10.1007/3-540-44614-1\_46}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/WolzK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/YamaguchiMMH00, author = {Yoshiki Yamaguchi and Akira Miyashita and Tsutomu Maruyama and Tsutomu Hoshino}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Co-processor System with a Virtex {FPGA} for Evolutionary Computation}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {240--249}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_27}, doi = {10.1007/3-540-44614-1\_27}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/YamaguchiMMH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/YamamotoSKA00, author = {Ou Yamamoto and Yuichiro Shibata and Hitoshi Kurosawa and Hideharu Amano}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {475--484}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_52}, doi = {10.1007/3-540-44614-1\_52}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/YamamotoSKA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ZhangNL00, author = {Xue{-}Jie Zhang and Kam{-}Wing Ng and Wayne Luk}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {361--370}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_39}, doi = {10.1007/3-540-44614-1\_39}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ZhangNL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ZhuM00, author = {Jihan Zhu and George J. Milne}, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Implementing Kak Neural Networks on a Reconfigurable Computing Platform}, booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, pages = {260--269}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1\_29}, doi = {10.1007/3-540-44614-1\_29}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ZhuM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/fpl/2000, editor = {Reiner W. Hartenstein and Herbert Gr{\"{u}}nbacher}, title = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, {FPL} 2000, Villach, Austria, August 27-30, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1896}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-44614-1}, doi = {10.1007/3-540-44614-1}, isbn = {3-540-67899-9}, timestamp = {Tue, 14 May 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/2000.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.