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Publication search results
found 98 matches
- 2024
- Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su:
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2344-2348 (2024) - Oussama Azzouzi, Mohamed Anane, Mouloud Koudil, Mohamed Issad, Yassine Himeur:
Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA. J. Supercomput. 80(2): 2633-2659 (2024) - 2023
- Argyrios Sideris, Theodora Sanida, Minas Dasygenis:
A Novel Hardware Architecture for Enhancing the Keccak Hash Function in FPGA Devices. Inf. 14(9): 475 (2023) - Medien Zeghid, Hassan Yousif Ahmed, Abdellah Chehri, Anissa Sghaier:
Speed/Area-Efficient ECC Processor Implementation Over GF(2m) on FPGA via Novel Algorithm-Architecture Co-Design. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1192-1203 (2023) - Oussama Azzouzi, Mohamed Anane, Mouloud Koudil, Mohamed Issad, Yassine Himeur:
Novel Area-Efficient and Flexible Architectures for Optimal Ate Pairing on FPGA. CoRR abs/2308.04261 (2023) - 2022
- Sagarika Behera, Prathuri Jhansi Rani:
Design of Novel Hardware Architecture for Fully Homomorphic Encryption Algorithms in FPGA for Real-Time Data in Cloud Computing. IEEE Access 10: 131406-131418 (2022) - Senthil Kumaran Varadharajan, Viswanathan Nallasamy:
P-SCADA - A novel area and energy efficient FPGA architectures for LSTM prediction of heart arrthymias in biot applications. Expert Syst. J. Knowl. Eng. 39(3) (2022) - Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti:
A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1672-1676 (2022) - Sina Ghaffari, David W. Capson, Kin Fun Li:
A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern. IEEE Trans. Very Large Scale Integr. Syst. 30(6): 826-839 (2022) - Daniel Song, Eugene Wu, William Song, Bow-Nan Cheng:
Resource-Efficient and Power-Efficient FPGA Frequency Channelizer Using Novel Systolic Array Architectures. MILCOM 2022: 735-742 - 2021
- Han Jia, Daming Ren, Xuecheng Zou:
An FPGA-based accelerator for deep neural network with novel reconfigurable architecture. IEICE Electron. Express 18(4): 20210012 (2021) - Kaveh Akbarzadeh-Sherbaf, Mikaeel Bahmani, Danial Ghiaseddin, Saeed Safari, AbdolHossein Vahabie:
A Novel Approximate Hamming Weight Computing for Spiking Neural Networks: an FPGA Friendly Architecture. CoRR abs/2104.14594 (2021) - (Withdrawn) A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGA. J. Ambient Intell. Humaniz. Comput. 12(7): 7263-7271 (2021)
- 2020
- Gomathi Swaminathan, G. Murugesan, S. Sasikala, L. Murali:
A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA. Microprocess. Microsystems 74: 103018 (2020) - Vladimir Rybalkin, Norbert Wehn:
When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network. FPGA 2020: 111-121 - Kaichuang Shi, Hao Zhou, Xuegong Zhou, Lingli Wang:
GIB: A Novel Unidirectional Interconnection Architecture for FPGA. FPT 2020: 174-181 - Cristian Ignat, Paul Faragó, Sorin Hintea:
FPGA Implementation of a Novel Dual - BRAM Processor Architecture. TSP 2020: 124-128 - 2019
- Leandro D. Medus, Taras Iakymchuk, José Vicente Francés-Víllora, Manuel Bataller-Mompeán, Alfredo Rosado Muñoz:
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks. IEEE Access 7: 76084-76103 (2019) - K. Sathish Shet, A. R. Aswath, M. C. Hanumantharaju, Xiao-Zhi Gao:
Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography. Multim. Tools Appl. 78(13): 18309-18338 (2019) - Jie Lei, Lingyun Wu, Yunsong Li, Weiying Xie, Chein-I Chang, Jintao Zhang, Biying Huang:
A Novel FPGA-Based Architecture for Fast Automatic Target Detection in Hyperspectral Images. Remote. Sens. 11(2): 146 (2019) - Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama:
A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC 2019: 74-80 - Jo Vliegen, Md Masoom Rabbani, Mauro Conti, Nele Mentens:
A Novel FPGA Architecture and Protocol for the Self-attestation of Configurable Hardware. IACR Cryptol. ePrint Arch. 2019: 405 (2019) - 2018
- Carlos González, Sebastián López, Daniel Mozos, Roberto Sarmiento:
A novel FPGA-based architecture for the estimation of the virtual dimensionality in remotely sensed hyperspectral images. J. Real Time Image Process. 15(2): 297-308 (2018) - 2017
- Sridevi Arumugam, Lakshmiprabha Viswanaathan:
A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture. Int. J. Circuit Theory Appl. 45(4): 550-570 (2017) - Radek Isa, Jirí Matousek:
A novel architecture for LZSS compression of configuration bitstreams within FPGA. DDECS 2017: 171-176 - John Darvill, Alin Tisan, Marcian N. Cirstea:
A novel ANFIS algorithm architecture for FPGA implementation. ISIE 2017: 1243-1248 - 2016
- Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40: 16-26 (2016) - Carlos Andres Lara-Nino, Miguel Morales-Sandoval, Arturo Diaz-Perez:
Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher. DSD 2016: 646-650 - Umer Farooq, Muhammad Khurram Bhatti, M. Hassan Aslam:
A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach. DTIS 2016: 1-6 - Grace Zgheib, Paolo Ienne:
Automatic wire modeling to explore novel FPGA architectures. FPT 2016: 181-184
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