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Publication search results
found 63 matches
- 2020
- Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. IPSJ Trans. Syst. LSI Des. Methodol. 13: 35-38 (2020) - 2019
- Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi:
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12: 78-80 (2019) - Hiroki Koyasu, Yasuhiro Takahashi:
Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 12: 50-52 (2019) - Shinichi Takagi, Kimihiko Kato, Kei Sumita, Kwangwon Jo, Cheol-Min Lim, Ryotaro Takaguchi, Dae-Hwan Ahn, Jun Takeyasu, Kasidit Toprasertpong, Mitsuru Takenaka:
Advanced MOS Device Technology for Low Power Logic LSI. MIXDES 2019: 26-33 - 2018
- Shinichi Takagi, Kimihiko Kato, Wu-Kang Kim, Kwangwon Jo, Ryo Matsumura, Ryotaro Takaguchi, Dae-Hwan Ahn, Takahiro Gotow, Mitsuru Takenaka:
MOS Device Technology using Alternative Channel Materials for Low Power Logic LSI. ESSDERC 2018: 6-11 - 2017
- Saurabh Gupta, Jennifer Dworak, Daniel Engels, Al Crouch:
Mitigating simple power analysis attacks on LSIB key logic. NATW 2017: 1-6 - 2016
- Michitarou Yabuuchi, Kazutoshi Kobayashi:
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. IPSJ Trans. Syst. LSI Des. Methodol. 9: 72-78 (2016) - 2015
- Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu:
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL 2015: 152-157 - Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine:
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS 2015: 1-4 - 2014
- Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. ISCAS 2014: 826-829 - Masanori Natsui, Takahiro Hanyu:
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS 2014: 468 - 2013
- Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi:
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS 2013: 105-109 - 2012
- Taiga Takata, Yusuke Matsunaga:
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 55-62 (2012) - Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. IEEE J. Solid State Circuits 47(7): 1776-1783 (2012) - Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine:
LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. 43(4): 244-249 (2012) - Natsuki Kai, Ryoji Nishinohara, Hiroshi Koide:
A SIMD Parallelization Method for an Application for LSI Logic Simulation. ICPP Workshops 2012: 375-381 - 2011
- Hiroaki Yoshida, Masahiro Fujita:
Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. IPSJ Trans. Syst. LSI Des. Methodol. 4: 70-79 (2011) - Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202 - 2010
- Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara:
Approximate Model Checking Using a Subset of First-order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3: 268-282 (2010) - Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3: 105-117 (2010) - 2008
- Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara:
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Trans. Electron. 91-C(8): 1338-1347 (2008) - 2007
- Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi:
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. 90-C(10): 1892-1899 (2007) - Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi:
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Trans. Electron. 90-C(5): 1129-1137 (2007) - 2005
- Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects. J. Multiple Valued Log. Soft Comput. 11(5-6): 545-565 (2005) - 2004
- Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Hideyuki Tsuboi, Yuichi Okuyama, Akira Nagoya:
Dynamically Reconfigurable Logic LSI: PCA-2. IEICE Trans. Inf. Syst. 87-D(8): 2011-2020 (2004) - 2000
- Masakazu Yamashina, Masato Motomura:
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. ASP-DAC 2000: 329-332 - Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina:
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC 2000: 151-154 - Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda:
Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond. ICCD 2000: 556-558 - 1999
- Koji Inoue, Koji Kai, Kazuaki J. Murakami:
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222
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