Malgorzata Marek-Sadowska

◀ ▶ joint publications with Kai Wang 0011

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Publications

2005
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Kai Wang, Malgorzata Marek-Sadowska:
On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 407-417 (2005)
[j47]
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Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska:
General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 773-782 (2005)
[c124]
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  - conf/glvlsi/JiangWM05
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Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska:
Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI 2005: 332-336
2004
[j42]
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  - journals/tcad/ChangHHWMCC04
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Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen:
Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 102-118 (2004)
[c114]
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Kai Wang, Malgorzata Marek-Sadowska:
Buffer sizing for clock power minimization subject to general skew constraints. DAC 2004: 159-164
[c107]
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  - conf/iccd/WangM04
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Kai Wang, Malgorzata Marek-Sadowska:
Potential Slack Budgeting with Clock Skew Optimization. ICCD 2004: 265-271
[c105]
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Kai Wang, Malgorzata Marek-Sadowska:
Clock network sizing via sequential linear programming with time-domain analysis. ISPD 2004: 182-189
2003
[c102]
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Kai Wang, Malgorzata Marek-Sadowska:
On-chip power supply network optimization using multigrid-based technique. DAC 2003: 113-118
[c96]
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Kai Wang, Malgorzata Marek-Sadowska:
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. DATE 2003: 10850-10855
2002
[c83]
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  - conf/date/MukherjeeWCM02
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Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska:
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. DATE 2002: 176-183
2001
[c74]
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  - conf/dac/ChangWM01
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Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska:
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. DAC 2001: 97-102

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