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Yongpan Liu
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Publications
- 2024
- [j85]Jinshan Yue, Yongpan Liu, Xiaoyu Feng, Yifan He, Jingyu Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang, Nan Sun, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang:
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. IEEE J. Solid State Circuits 59(5): 1612-1627 (2024) - [j82]Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu:
LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 852-856 (2024) - [c142]Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. ISSCC 2024: 578-580 - 2023
- [j72]Yifan He, Jinshan Yue, Xiaoyu Feng, Yuxuan Huang, Hongyang Jia, Jingyu Wang, Lu Zhang, Wenyu Sun, Huazhong Yang, Yongpan Liu:
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 416-420 (2023) - [j71]Lu Zhang, Dejun Mu, Yuxuan Huang, Jingyu Wang, Yifan He, Yaolei Li, Lizhou Liu, Kaiwei Zou, Huazhong Yang, Yongpan Liu:
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1124-1128 (2023) - [j70]Yaolei Li, Jinshan Yue, Jingyu Wang, Chen Tang, Yifan He, Wenbin Jia, Kaiwei Zou, Lu Zhang, Huazhong Yang, Yongpan Liu:
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1179-1183 (2023) - [j68]Songming Yu, Yifan He, Hongyang Jia, Wenyu Sun, Mufeng Zhou, Luchang Lei, Wentao Zhao, Guofu Ma, Huazhong Yang, Yongpan Liu:
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3099-3103 (2023) - [c130]Zi Wang, Jinshan Yue, Chaojie He, Zhuoyu Dai, Feibin Xiang, Zhaori Cong, Yifan He, Xiaoyu Feng, Yongpan Liu:
A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. ISCAS 2023: 1-5 - [c129]Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC 2023: 130-131 - [c128]Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu:
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. ISSCC 2023: 252-253 - [c125]Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu:
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j66]Yi Li, Woyu Zhang, Xiaoxin Xu, Yifan He, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Shaocong Wang, Chunmeng Dou, Yongpan Liu, Zhongrui Wang, Dashan Shang:
Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory. Adv. Intell. Syst. 4(8) (2022) - [j65]Yi Li, Woyu Zhang, Xiaoxin Xu, Yifan He, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Shaocong Wang, Chunmeng Dou, Yongpan Liu, Zhongrui Wang, Dashan Shang:
Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory. Adv. Intell. Syst. 4(8) (2022) - [j63]Jinshan Yue, Yongpan Liu, Zhe Yuan, Xiaoyu Feng, Yifan He, Wenyu Sun, Zhixiao Zhang, Xin Si, Ruhui Liu, Zi Wang, Meng-Fan Chang, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang:
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. IEEE J. Solid State Circuits 57(8): 2560-2573 (2022) - [j60]Yuxuan Huang, Yifan He, Jinshan Yue, Huazhong Yang, Yongpan Liu:
Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 518-529 (2022) - [j59]Yuxuan Huang, Yifan He, Jingyu Wang, Jinshan Yue, Lu Zhang, Kaiwei Zou, Huazhong Yang, Yongpan Liu:
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3144-3148 (2022) - [c122]Yuxuan Huang, Yifan He, Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu:
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC. ASP-DAC 2022: 684-689 - [c118]Yifan He, Yuxuan Huang, Jinshan Yue, Wenyu Sun, Lu Zhang, Yongpan Liu:
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations. ISCAS 2022: 3279-3283 - 2021
- [c117]Yuxuan Huang, Yifan He, Jinshan Yue, Huazhong Yang, Yongpan Liu:
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC. ASP-DAC 2021: 126-131 - [c116]Yifan He, Jinshan Yue, Yongpan Liu, Huazhong Yang:
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules. ASP-DAC 2021: 813-818 - [c106]Jinshan Yue, Xiaoyu Feng, Yifan He, Yuxuan Huang, Yipeng Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu:
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. ISSCC 2021: 238-240 - 2020
- [c93]Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. ISSCC 2020: 234-236
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last updated on 2024-05-06 23:03 CEST by the dblp team
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