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Chiou-Yng Lee
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Publications
- 2019
- [j56]Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao:
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2119-2130 (2019) - [c34]Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher:
Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. ISCAS 2019: 1-5 - 2018
- [j52]Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee:
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4(4): 773-783 (2018) - 2017
- [j49]Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan:
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 735-746 (2017) - 2016
- [j48]Chiou-Yng Lee, Pramod Kumar Meher:
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm". IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1316-1319 (2016) - [j47]Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu:
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2413-2425 (2016) - 2015
- [j44]Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 854-862 (2015) - [j43]Chiou-Yng Lee, Pramod Kumar Meher:
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1091-1098 (2015) - [j42]Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2044-2051 (2015) - [j41]Chiou-Yng Lee, Pramod Kumar Meher:
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2846-2855 (2015) - [c25]Jeng-Shyang Pan, Pramod Kumar Meher, Chiou-Yng Lee, Hong-Hai Bai:
Efficient subquadratic parallel multiplier based on modified SPB of GF(2m). ISCAS 2015: 1430-1433 - 2014
- [j36]Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan:
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3115-3124 (2014) - [j35]Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang:
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3125-3134 (2014) - [c24]Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee:
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. ISIC 2014: 176-179 - 2013
- [j32]Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher:
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3195-3204 (2013) - 2011
- [c18]Chiou-Yng Lee, Pramod Kumar Meher:
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. ICGEC 2011: 232-236 - 2010
- [j25]Chiou-Yng Lee, Pramod Kumar Meher:
Efficient bit-parallel multipliers over finite fields GF(2m). Comput. Electr. Eng. 36(5): 955-968 (2010) - [j22]Chiou-Yng Lee, Pramod Kumar Meher, Jagdish Chandra Patra:
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1234-1238 (2010) - 2009
- [c12]Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee:
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. ASP-DAC 2009: 210-215 - [c11]Pramod Kumar Meher, Chiou-Yng Lee:
Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition. ISCAS 2009: 2910-2913 - 2008
- [c8]Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Bit-Parallel Multipliers in Composite Fields. APSCC 2008: 686-691
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