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Christos A. Papachristou
Publications
- 2002
- [j18]Mehrdad Nourani, Christos A. Papachristou:
False path exclusion in delay analysis of RTL structures. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 30-43 (2002) - 2001
- [j17]Mehrdad Nourani, Joan Carletta, Christos A. Papachristou:
Integrated test of interacting controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 6(3): 401-422 (2001) - 2000
- [j16]Mehrdad Nourani, Christos A. Papachristou:
Stability-based algorithms for high-level synthesis of digital ASICs. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 431-435 (2000) - [c65]Mehrdad Nourani, Joan Carletta, Christos A. Papachristou:
Synthesis-for-testability of controller-datapath pairs that use gated clocks. DAC 2000: 613-618 - [c64]Joan Carletta, Christos A. Papachristou, Mehrdad Nourani:
Detecting Undetectable Controller Faults Using Power Analysis. DATE 2000: 723-728 - [c63]Mehrdad Nourani, Christos A. Papachristou:
An ILP formulation to optimize test access mechanism in system-on-chip testing. ITC 2000: 902-910 - 1999
- [j15]Mehrdad Nourani, Christos A. Papachristou:
Structural Fault Testing of Embedded Cores Using Pipelining. J. Electron. Test. 15(1-2): 129-144 (1999) - [j14]Christos A. Papachristou, Mehrdad Nourani, Mark Spining:
A multiple clocking scheme for low-power RTL design. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 266-276 (1999) - [c61]Christos A. Papachristou, F. Martin, Mehrdad Nourani:
Microprocessor Based Testing for Core-Based System on Chip. DAC 1999: 586-591 - [c60]Joan Carletta, Mehrdad Nourani, Christos A. Papachristou:
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. DATE 1999: 278-282 - 1998
- [c55]Mehrdad Nourani, Christos A. Papachristou:
A Bypass Scheme for Core-Based System Fault Testing. DATE 1998: 979-980 - [c54]Mehrdad Nourani, Christos A. Papachristou:
Parallelism in Structural Fault Testing of Embedded Cores. VTS 1998: 15-21 - 1997
- [c52]Mehrdad Nourani, Joan Carletta, Christos A. Papachristou:
A Scheme for Integrated Controller-Datapath Fault Testing. DAC 1997: 546-551 - [c51]Mehrdad Nourani, Christos A. Papachristou:
Structural BIST insertion using behavioral test analysis. ED&TC 1997: 64-68 - 1996
- [c45]Christos A. Papachristou, Mark Spining, Mehrdad Nourani:
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. DAC 1996: 337-342 - [c42]Christos A. Papachristou, Mehrdad Nourani:
False path exclusion in delay analysis of RTL-based datapath-controller designs. EURO-DAC 1996: 336-341 - 1995
- [c36]Christos A. Papachristou, Mark Spining, Mehrdad Nourani:
A multiple clocking scheme for low power RTL design. ISLPD 1995: 27-32 - 1993
- [c32]Mehrdad Nourani, Christos A. Papachristou:
A Layout Estimation Algorithm for RTL Datapaths. DAC 1993: 285-291 - [c31]Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani:
An Approach for Redesigning in Data Path Synthesis. DAC 1993: 419-423 - 1992
- [c27]Mehrdad Nourani, Christos A. Papachristou:
Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. DAC 1992: 99-105 - [c26]Mehrdad Nourani, Christos A. Papachristou, Yoshiyasu Takefuji:
A neural network based algorithm for the scheduling problem in high-level synthesis. EURO-DAC 1992: 341-346 - [c25]Haidar Harmanani, Christos A. Papachristou, Scott Chiu, Mehrdad Nourani:
SYNTEST: an environment for system-level design for test. EURO-DAC 1992: 402-407
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