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Chris R. Jesshope
- > Home > Persons > Chris R. Jesshope
Publications
- 2014
- [j34]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Cache-based high-level simulation of microthreaded many-core architectures. J. Syst. Archit. 60(7): 529-552 (2014) - [j33]Qiang Yang, Jian Fu, Raphael Poss, Chris R. Jesshope:
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. ACM Trans. Embed. Comput. Syst. 13(3s): 103:1-103:21 (2014) - [c56]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. ARES 2014: 88-93 - [c55]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
A fault detection mechanism in a Data-flow scheduled Multithreaded processor. DATE 2014: 1-4 - [c54]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Analytical-Based High-Level Simulation of the Microthreaded Many-Core Architectures. PDP 2014: 344-351 - [c53]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Signature-based high-level simulation of microthreaded many-core architectures. SIMULTECH 2014: 509-516 - 2013
- [j32]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope:
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. Microprocess. Microsystems 37(8-C): 1090-1101 (2013) - [c52]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - A simulation environment for multi-core research and education. ICSAMOS 2013: 80-87 - [c51]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
On-demand thread-level fault detection in a concurrent programming environment. ICSAMOS 2013: 255-262 - [i1]Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013) - 2012
- [c50]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope:
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508 - [c49]Muhammad Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss:
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores. RAPIDO 2012: 1-8 - 2010
- [c44]Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphael Poss:
Resource-Agnostic Programming for Many-Core Microgrids. Euro-Par Workshops 2010: 109-116 - 2009
- [c39]Chris R. Jesshope, Michael A. Hicks, Mike Lankamp, Raphael 'kena' Poss, Li Zhang:
Making multi-cores mainstream - from security to scalability. PARCO 2009: 16-31
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