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ORCIDYi-Hau Chen
- > Home > Persons > Yi-Hau Chen
Publications
- 2010
[j6]Tzu-Der Chuang, Yu-Jen Chen, Yi-Hau Chen, Shao-Yi Chien
, Liang-Gee Chen:
Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension. J. Signal Process. Syst. 60(3): 363-375 (2010)- [c13]Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen, Liang-Gee Chen:
Low bandwidth decoder framework for H.264/AVC scalable extension. ISCAS 2010: 2960-2963 - [c12]Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen, Liang-Gee Chen:
A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications. ISSCC 2010: 330-331 - 2009
- [c11]Tzu-Der Chuang, Lo-Mei Chang, Tsai-Wei Chiu, Yi-Hau Chen, Liang-Gee Chen:
Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control. ICASSP 2009: 2009-2012 - 2008
- [j5]Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching-Yeh Chen, Shao-Yi Chien, Liang-Gee Chen:
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine. IEEE Trans. Circuits Syst. Video Technol. 18(1): 98-109 (2008) - [j4]Yi-Hau Chen, Shao-Yi Chien, Ching-Yeh Chen, Yu-Wen Huang, Liang-Gee Chen:
Analysis and Hardware Architecture Design of Global Motion Estimation. J. Signal Process. Syst. 53(3): 285-300 (2008) - [j3]Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen:
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC. J. Signal Process. Syst. 53(3): 335-347 (2008) - [c10]Yi-Hau Chen, Tzu-Der Chuang, Yu-Han Chen, Chen-Han Tsai, Liang-Gee Chen:
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder. ISCAS 2008: 29-32 - 2007
- [c9]Yu-Jen Chen, Yi-Hau Chen, Tzu-Der Chuang, Chung-Te Li, Shao-Yi Chien, Liang-Gee Chen:
Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension. SiPS 2007: 515-520 - [c8]Yi-Hau Chen, Chia-Hua Lin, Ching-Yeh Chen, Liang-Gee Chen:
Fast prediction algorithm of adaptive GOP structure for SVC. VCIP 2007: 65080U - 2006
- [j2]Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Liang-Gee Chen:
Level C+ data reuse scheme for motion estimation with corresponding coding orders. IEEE Trans. Circuits Syst. Video Technol. 16(4): 553-558 (2006) - [j1]Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Shao-Yi Chien, Liang-Gee Chen:
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering. IEEE Trans. Signal Process. 54(10): 4004-4014 (2006) - [c7]Yi-Hau Chen, Ching-Yeh Chen, Chih-Chi Cheng, Liang-Gee Chen:
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME. ICME 2006: 365-368 - [c6]Ching-Yeh Chen, Yi-Hau Chen, Chih-Chi Cheng, Liang-Gee Chen:
Frame-level data reuse for motion-compensated temporal filtering. ISCAS 2006 - [c5]Chih-Chi Cheng, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen:
Analysis and VLSI architecture of update step in motion-compensated temporal filtering. ISCAS 2006 - 2005
- [c4]Chao-Tsung Huang, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen:
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications]. ICASSP (5) 2005: 93-96 - [c3]Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Chung-Jr Lian, Liang-Gee Chen:
System analysis of VLSI architecture for motion-compensated temporal filtering. ICIP (3) 2005: 992-995 - [c2]Yi-Hau Chen, Ching-Yeh Chen, Liang-Gee Chen:
Architecture of global motion compensation for MPEG-4 advanced simple profile. ISCAS (5) 2005: 1798-1801 - 2003
- [c1]Ching-Yeh Chen, Shao-Yi Chien, Yi-Hau Chen, Yu-Wen Huang, Liang-Gee Chen:
Unsupervised object-based sprite coding system for tennis sport. ICME 2003: 337-340
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