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ORCIDAkira Tsuchiya
- > Home > Persons > Akira Tsuchiya
Publications
- 2024
[j25]Toshiyuki Inoue
, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. 145: 106120 (2024)- [j24]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura:
A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2514-2518 (2024) - [c59]Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC 2024: 1-4 - 2023
- [j23]Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express 20(14): 20230238 (2023) - [j22]Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express 20(18): 20230339 (2023) - [c58]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON 2023: 1-2 - [c57]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS 2023: 1-4 - [c56]Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC 2023: 13-14 - 2022
- [c55]Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. ASP-DAC 2022: 96-97 - [c54]Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine:
Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems. ICEIC 2022: 1-4 - [c53]Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine:
A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver. ICEIC 2022: 1-4 - [c52]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura:
Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC 2022: 1-4 - [c51]Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine:
Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion. ICEIC 2022: 1-4 - [c50]Masataka Inoue, Shinya Nakashioya, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band. ICECS 2022 2022: 1-4 - [c49]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 2022: 1-4 - [c48]Masanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA. ISOCC 2022: 55-56 - [c47]Yuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Smart Computational Resource Distribution System with Automatic Classification Interface for CPS. ISOCC 2022: 101-102 - [c46]Shungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing. ISOCC 2022: 338-339 - [c45]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS 2022: 1-4 - [c44]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura:
A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS 2022: 1-4 - 2021
- [c43]Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. ASP-DAC 2021: 15-16 - [c42]Yudai Ichii, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS. ICEIC 2021: 1-4 - [c41]Ukyo Yoshimura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA. ICEIC 2021: 1-4 - [c40]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS 2021: 1-6 - 2020
- [c39]Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Processing Time Reduction for JPEG Compression Using Pixel Array Conversion. ISOCC 2020: 111-112 - 2019
- [j20]Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera:
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. IEICE Trans. Electron. 102-C(7): 573-579 (2019) - [c38]Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara, Keiji Kishine:
Optimization Technique of Memory Traffic for FPGA-Based Image Processing System. ISOCC 2019: 46-47 - [c37]Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Frequency Discriminator Using a Simple AD Converter for Interface Systems. ISOCC 2019: 128-129 - [c36]Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS. ISOCC 2019: 210-211 - [c34]Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine:
Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. SoCC 2019: 161-164 - 2018
- [c32]Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion. ICECS 2018: 49-52 - [c31]Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. MWSCAS 2018: 751-754 - [c30]Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka:
A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS. VLSI-DAT 2018: 1-4 - 2017
- [c29]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura:
Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS. ISOCC 2017: 77-78 - [c28]Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Compact implementation IIR filter in FPGA for noise reduction of sensor signal. ISOCC 2017: 258-259 - [c27]Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
FPGA-based transceiver circuit for labeling signal transmission system. ISOCC 2017: 310-311 - 2016
- [c25]Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya:
36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. ISOCC 2016: 61-62 - 2015
- [j18]Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera:
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1288-1295 (2015) - 2014
- [c21]Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai:
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS 2014: 2704-2707 - 2013
- [c20]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. ASP-DAC 2013: 105-106 - 2012
- [j14]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 479-486 (2012) - [c18]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. ASP-DAC 2012: 561-562 - 2011
- [c16]Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera:
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. ISOCC 2011: 36-39 - [c15]Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. ISOCC 2011: 223-226 - 2010
- [c14]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. CICC 2010: 1-4
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