Sergio Cuenca-Asensi

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Fernanda Lima Kastensmidt

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Publications

2018
[j17]
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Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt:
Design of approximate-TMR using approximate library and heuristic approaches. Microelectron. Reliab. 88-90: 898-902 (2018)
[c29]
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  - conf/latw/GomesSSMMCK18
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Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt:
Improving approximate-TMR using multi-objective optimization genetic algorithm. LATS 2018: 1-6
2016
[c22]
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  - conf/latw/ChielleDKCSR16
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Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda:
Hybrid soft error mitigation techniques for COTS processor-based systems. LATS 2016: 99-104
2015
[j10]
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  - journals/et/Restrepo-CalleC15
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Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Eduardo Chielle, Fernanda Lima Kastensmidt:
Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors. J. Electron. Test. 31(2): 139-150 (2015)
[c20]
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Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Fernanda Lima Kastensmidt:
Considerations on application of selective hardening based on software fault tolerance techniques. LATS 2015: 1-6
2014
[c19]
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  - conf/latw/Restrepo-CalleCMCK14
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Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Eduardo Chielle, Fernanda Lima Kastensmidt:
Efficient metric for register file criticality in processor-based systems. LATW 2014: 1-6
[c18]
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  - conf/patmos/ChielleKC14
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Eduardo Chielle, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi:
Tuning software-based fault-tolerance techniques for power optimization. PATMOS 2014: 1-7

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