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ORCID19th LATS 2018: Sao Paulo, Brazil
- 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018. IEEE 2018, ISBN 978-1-5386-1472-3
Session 1: Reliability Analysis in SoCs
- Fabio Benevenuti, Fernanda Lima Kastensmidt:
Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC. 1-6 - Israel C. Lopes, Fabio Benevenuti, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Paolo Rech
:
Reliability analysis on case-study traffic sign convolutional neural network on APSoC. 1-6 - Rodrigo Travessini, Paulo Ricardo Cechelero Villa, Fabian Luis Vargas, Eduardo Augusto Bezerra:
Processor core profiling for SEU effect analysis. 1-6
Session 2: Manufacturing Test and Silicon Validation
- Dionisio de Carvalho, Bruno Sanches, M. De Carvalho, Wilhelmus A. M. Van Noije:
A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests. 1-6 - Eduardo Garcia-Espinosa, Omar Longoria-Gandara, Enrique Gonzalez-Garcia, Arturo Veloz-Guerrero:
Post-silicon validation based on synthetic test patterns for early detection of timing anomalies. 1-5 - Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Direct optimization of a PCI express link equalization in industrial post-silicon validation. 1-6
Session 3: Fault Tolerant Architectures
- Stefano Esposito, Serhiy Avramenko, Massimo Violante:
RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC. 1-6 - Paulo Vinicius Cardoso, Patrícia Pitthan Barcelos:
Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenarios. 1-6 - Alexander Aponte-Moreno, Alejandro Moncada, Felipe Restrepo-Calle, Cesar Augusto Pedraza:
A review of approximate computing techniques towards fault mitigation in HW/SW systems. 1-6
Session 4: Fault Injection Strategies
- Carlos L. G. Batista, Eliane Martins, Maria de Fátima Mattiello-Francisco:
On the use of a failure emulator mechanism at nanosatellite subsystems integration tests. 1-6 - Fábio B. Armelin, Lírida A. B. Naviner, Roberto d'Amore:
Using FPGA self-produced transients to emulate SETs for SER estimation. 1-3
Session 5: Exploring Redundancy for Fault Tolerant Systems
- Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen:
Fault masking ratio analysis of majority voters topologies. 1-6 - Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt:
Improving approximate-TMR using multi-objective optimization genetic algorithm. 1-6
Session 6: Test and Fault Tolerance in Memories
- Reinaldo Silveira, Qadeer Qureshi, Rodrigo Zeli:
Flexible architecture of memory BISTs. 1-6 - George Redivo Pinto, Guilherme Cardoso Medeiros, Fabian Vargas, Leticia Bolzani Poehls:
A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects. 1-6
Poster Session 1
- Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt:
Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits. 1-4 - Gabriel Natan P. Silva, Ricardo O. Duarte:
Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. 1-4 - Augusto Einsfeldt, Renato C. Giacomini:
Fault-tolerant architecture with full recovery under presence of SEU. 1-4 - Luiz Carlos Kretly, Ricardo Maltione, Marcelo Gradella Villalva:
A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA. 1-4 - Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas:
Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module). 1-4 - Joao de Moraes, Taisy Silva Weber, Guilherme Muller, Tiago Dall'Agnol, Rafael Macedo, Elaine P. L. Scartezzini, Roque Eduardo Dapper, Sérgio Luis Cechin, Joao Netto:
Architecture of an industrial analog input designed to meet safety requirements. 1-4
Session 7: Fault Tolerance Techniques
- Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Fabian Luis Vargas, Eduardo Augusto Bezerra:
Processor checkpoint recovery for transient faults in critical applications. 1-6 - Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection. 1-6 - Felix Mühlbauer, Lukas Schröder, Mario Schölzel:
A fault tolerant dynamically scheduled processor with partial permanent fault handling. 1-6
Session 8: Aging Modeling and Mitigation
- Andres F. Gomez, Roberto Gómez, Víctor H. Champac:
A metric-guided gate-sizing methodology for aging guardband reduction. 1-6 - Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui, Marco Rovatti:
Ionizing radiation modeling in DRAM transistors. 1-6
Session 9: Testing and Security of Microprocessor Cores
- Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda:
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications. 1-6 - Andrea Marcelli, Ernesto Sánchez, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti, Davide Pola, Alessandro Salvato, Michele Simili:
Defeating hardware Trojan in microprocessor cores through software obfuscation. 1-6
Session 10: Testing Techniques for Embedded Systems
- Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Testing approximate digital circuits: Challenges and opportunities. 1-6 - Renato Severo, Celso Maciel da Costa, Adriane Parraga, Debora Motta, Ivan Müller, Fabian Vargas:
Design and test of the RT-NKE task scheduling algorithm for multicore architectures. 1-6 - Stefano Esposito, Jacopo Sini, Massimo Violante:
Real-time validation of mixed-criticality applications. 1-6
Session 11: Testing of Analog Systems
- Hassen Aziza, Karine Coulié, Wenceslas Rahajandraibe, Remy Vauche:
Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chain. 1-5 - Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee:
Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. 1-6
Session 12: Dependable Embedded Systems
- Rafael Melo Macieira, Edna Barros:
TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications. 1-6 - Marcos Silveira Santos, Roberto d'Amore:
Error detection method for the ARINC429 communication. 1-6 - Alexandra Kourfali, Dirk Stroobandt:
Superimposed in-circuit debugging for self-healing FPGA overlays. 1-6
Poster Session 2
- Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Carlos Vazquez, Tinus Stander, Fortunato C. Dualibe:
Influence of passive oscillator component variation on OBT sensitivity in OTAs. 1-4 - Salem Abdennadher, Michael Altmann, Bin Xue:
Challenges and emerging solutions in testing HBM IO & systems. 1-4 - Jerrin Pathrose, Ghazanfar Ali, Hans G. Kerkhoff:
IJTAG compatible analogue embedded instruments for MPSoC life-time prediction. 1-4 - Fábio B. Armelin, Lirida A. B. Naviner, Roberto d'Amore:
Probability aware fault-injection approach for SER estimation. 1-3 - Juliano Oliveira, Marcilei Aparecida Guazzelli, Marco Antonio Assis, Renato C. Giacomini:
Single event effect: Simulations and analysis on 3N163 PMOS transistor. 1-3 - Lucas M. V. Pereira, Douglas R. Melo, Cesar A. Zeferino, Eduardo A. Bezerra:
Analysis of LEON3 systems integration for a Network-on-Chip. 1-3
Session 13: Electrical Characterization and PV Analysis
- Thales E. Becker, Fábio Fedrizzi Vidor, Gilson I. Wirth, Thorsten Meyers, Julia Reker, Ulrich Hilleringmann:
Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors. 1-6 - Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. 1-5 - G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen:
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs. 1-6
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