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Alberto Macii
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Publications
- 2014
- [j29]Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45(5): 530-538 (2014) - 2013
- [j28]Alessandro Sassone, Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. Microelectron. J. 44(11): 970-976 (2013) - [j27]Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino:
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 406-418 (2013) - 2012
- [j26]Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
On-chip process variation-tracking through an all-digital monitoring architecture. IET Circuits Devices Syst. 6(5): 366-373 (2012) - [j25]Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Design Techniques and Architectures for Low-Leakage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1992-2007 (2012) - [c64]Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Richard Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo:
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. DATE 2012: 165-166 - [c63]Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. PATMOS 2012: 155-165 - 2011
- [j24]Leandro Max de Lima Silva, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 242-253 (2011) - [c62]Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino:
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. DATE 2011: 1127-1128 - [c61]Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. PATMOS 2011: 162-172 - [c60]Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS 2011: 214-225 - 2010
- [c59]Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella:
An integrated thermal estimation framework for industrial embedded platforms. ACM Great Lakes Symposium on VLSI 2010: 293-298 - 2009
- [j17]Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1979-1993 (2009) - [c57]Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339 - [c56]Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS 2009: 1723-1726 - [c54]Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. PATMOS 2009: 227-236 - 2008
- [j15]Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino:
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. 4(3): 374-384 (2008) - [c52]Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino:
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303 - [c50]Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764 - 2007
- [c47]Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE 2007: 1544-1549 - [c46]Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504
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