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ORCIDDavide Bertozzi
- > Home > Persons > Davide Bertozzi
Publications
- 2013
[j22]Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich
, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi:
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12(4): 106:1-106:29 (2013)- 2012
- [c54]Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi:
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels. MCSoC 2012: 159-166 - 2011
- [c49]Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi:
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture. DATE 2011: 661-666 - [c48]Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi:
Mesochronous NoC technology for power-efficient GALS MPSoCs. INA-OCMC@HiPEAC 2011: 27-30 - [c45]Marco Ferraresi, Giuseppina Gobbo, Daniele Ludovici, Davide Bertozzi:
Bringing Network-on-Chip links to 45nm. SoC 2011: 122-127 - [c44]Hervé Tatenguem, Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Helmut Reinig:
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. NoCArc@MICRO 2011: 37-42 - [c43]Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi:
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. VLSI-SoC 2011: 308-313 - [e1]José Flich, Davide Bertozzi, Tor Skeie, Daniele Ludovici:
Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011. ACM 2011, ISBN 978-1-4503-0272-2 [contents] - 2010
- [c42]Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi:
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. DATE 2010: 679-684 - [c40]Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Francisco Gilabert Villamón, María Engracia Gómez, Davide Bertozzi:
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology. NoCArc@MICRO 2010: 37-42 - [c37]Alessandro Strano, Daniele Ludovici, Davide Bertozzi:
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design. ICSAMOS 2010: 20-27 - 2009
- [c36]Francisco Gilabert Villamón, Daniele Ludovici, Simone Medardoni, Davide Bertozzi, Luca Benini, Georgi Nedeltchev Gaydadjiev:
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints. CISIS 2009: 681-687 - [c35]Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi:
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. DATE 2009: 562-565 - [c33]Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini:
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip. ACM Great Lakes Symposium on VLSI 2009: 125-128 - [c30]Daniele Ludovici, Alessandro Strano, Davide Bertozzi:
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches. NoCArc@MICRO 2009: 31-36 - [c29]Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini, Georgi Gaydadjiev:
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. NOCS 2009: 244-249
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