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Paul Ampadu
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Publications
- 2011
- [p1]Paul Ampadu, Bo Fu, David Wolpert, Qiaoyan Yu:
Adaptive Voltage Control for Energy-Efficient NoC Links. Low Power Networks-on-Chip 2011: 45-69 - 2010
- [j10]Bo Fu, Paul Ampadu:
Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. IET Comput. Digit. Tech. 4(3): 251-261 (2010) - [j8]Bo Fu, Paul Ampadu:
Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 399-403 (2010) - [c22]David Wolpert, Bo Fu, Paul Ampadu:
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design. NOCS 2010: 107-114 - 2009
- [j4]Bo Fu, Paul Ampadu:
On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2042-2054 (2009) - [j3]Bo Fu, Paul Ampadu:
An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n. J. Signal Process. Syst. 56(1): 59-68 (2009) - [c18]Bo Fu, Paul Ampadu:
Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects. DFT 2009: 440-448 - [c16]Bo Fu, David Wolpert, Paul Ampadu:
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links. NOCS 2009: 54-63 - 2008
- [j1]Bo Fu, Paul Ampadu:
An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes. VLSI Design 2008: 109490:1-109490:14 (2008) - [c11]Bo Fu, Paul Ampadu:
A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects. NanoNet 2008: 74-79 - [c10]Bo Fu, Paul Ampadu:
A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes. SoCC 2008: 59-62 - 2007
- [c8]Bo Fu, Paul Ampadu:
Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency. ISCAS 2007: 1173-1176 - 2006
- [c5]Bo Fu, Qiaoyan Yu, Paul Ampadu:
Energy-delay minimization in nanoscale domino logic. ACM Great Lakes Symposium on VLSI 2006: 316-319 - [c4]Bo Fu, Paul Ampadu:
Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing. ICECS 2006: 1101-1104 - [c1]Bo Fu, Paul Ampadu:
Techniques for robust energy efficient subthreshold domino CMOS circuits. ISCAS 2006
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