Brian Young

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Tejasvi Anand

> Home > Persons > Brian Young

Publications

2017
[j11]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/TalegaonkarAEEN17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/TalegaonkarAEEN17
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52(9): 2306-2320 (2017)
2014
[j7]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/AnandETYH14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/AnandETYH14
Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits 49(10): 2243-2258 (2014)
[c16]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsic/TalegaonkarAEEN14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/TalegaonkarAEEN14
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC 2014: 1-2
[c15]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsic/YoungRREAH14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/YoungRREAH14
Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu:
A 75dB DR 50MHz BW 3^rd order CT-ΔΣ modulator using VCO-based integrators. VLSIC 2014: 1-2
2013
[c13]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/AnandTEYH13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/AnandTEYH13
Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC 2013: 256-257

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.