Paritosh Bhoraskar

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ahmed M. A. Ali

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Publications

2020
[j3]
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Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Matthew McShea, Joel Prabhakar, Scott Puckett:
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration. IEEE J. Solid State Circuits 55(12): 3210-3224 (2020)
[c4]
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Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Mohit Kumar, Matthew McShea, Ryan Bunch, Joel Prabhakar, Scott Puckett:
16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration. ISSCC 2020: 250-252
2016
[c3]
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Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor:
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. VLSI Circuits 2016: 1-2
2014
[j2]
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Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop:
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration. IEEE J. Solid State Circuits 49(12): 2857-2867 (2014)
[c2]
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Ahmed M. Abdelatty Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, David Jarman, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Ho-Young Lee:
29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration. ISSCC 2014: 482-483
2010
[j1]
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Ahmed M. A. Ali, Andrew S. Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Hüseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed:
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration. IEEE J. Solid State Circuits 45(12): 2602-2612 (2010)
[c1]
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Ahmed M. A. Ali, Andy Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed:
A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration. ISSCC 2010: 292-293

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