Volume 26, Number 1, January-February 2006

Editor-in-Chief's Message

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  Pradip Bose: Measuring the impact of microarchitectural ideas. 5-6

Micro Economics

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  Shane Greenstein: Format wars all over again. 7, 140

Features

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  Josep Torrellas: Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. 8-9
• 
  Onur Mutlu, Hyesoon Kim, Yale N. Patt: Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. 10-20
• 
  Ibrahim Hur, Calvin Lin: Adaptive History-Based Memory Schedulers for Modern Processors. 22-29
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  Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad Lai: Scalable Load and Store Processing in Latency-Tolerant Processors. 30-39
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  Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu: Tolerating Cache-Miss Latency with Multipass Pipelines. 40-47
• 
  Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark: Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. 48-58
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  C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie: Unbounded Transactional Memory. 59-69
• 
  Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi: Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. 70-79
• 
  Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas: Energy-Efficient Thread-Level Speculation. 80-91
• 
  Mohamed A. Gomaa, T. N. Vijaykumar: Opportunistic Transient-Fault Detection. 92-99
• 
  Satish Narayanasamy, Gilles Pokam, Brad Calder: BugNet: Recording Application-Level Execution for Deterministic Replay Debugging. 100-109
• 
  Lin Tan, Timothy Sherwood: Architectures for Bit-Split String Scanning in Intrusion Detection. 110-117
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  Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks: Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. 119-129
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  Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha: Temperature-Aware On-Chip Networks. 130-139

Micro Review

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  Richard Mateosian: The future will soon be here. 141-142

Micro Innovations

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  Philip G. Emma: How to write a patent. 144

Volume 26, Number 2, March-April 2006

Editor-in-Chief's Message

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  Pradip Bose: Workload characterization: A key aspect of microarchitecture design. 5-6

Micro Economics

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  Shane Greenstein: Andy's acceleration and Moore's momentum. 7

Features

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  John Sell, Alan Jay Smith: Guest Editors' Introduction: Hot Chips 17. 8-9
• 
  Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki: Synergistic Processing in Cell's Multicore Architecture. 10-24
• 
  Jeff Andrews, Nick Baker: Xbox 360 System Architecture. 25-37
• 
  Boris Murmann: Digitally Assisted Analog Circuits. 38-47
• 
  Volker Lindenstruth: An Extreme Processor for an Extreme Experiment. 48-57
• 
  Cary Gunn: CMOS Photonics for High-Speed Interconnects. 58-66
• 
  Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. 68-80

Micro Innovations

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  Philip G. Emma: The best patents of all. 83-84

Volume 26, Number 3, May-June 2006

Editor-in-Chief's Message

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  Pradip Bose: Robust On-Chip Communication. 5

Micro Economics

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  Shane Greenstein: Room for a Thousand Flowers to Bloom. 6, 93

Features

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  Fabrizio Petrini, Olav Lysne, Ron Brightwell: Guest Editors' Introduction: High-Performance Interconnects. 7-9
• 
  Michael Kistler, Michael Perrone, Fabrizio Petrini: Cell Multiprocessor Communication Network: Built for Speed. 10-23
• 
  Pavan Balaji, Wu-chun Feng, Dhabaleswar K. Panda: Bridging the Ethernet-Ethernot Performance Gap. 24-40
• 
  Ron Brightwell, Kevin T. Pedretti, Keith D. Underwood, Trammell Hudson: SeaStar Interconnect: Balanced Bandwidth for Scalable Performance. 41-57
• 
  Cyriel Minkenberg, François Abel, Peter Müller, Raj Krishnamurthy, Mitchell Gusat, Peter Dill, Ilias Iliadis, Ronald P. Luijten, B. Roe Hemenway, Richard Grzybowski, Enrico Schiattarella: Designing a Crossbar Scheduler for HPC Applications. 58-71
• 
  Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer: A Network Processor-Based, Content-Aware Switch. 72-84

Micro Review

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  Richard Mateosian: More on Old Topics. 86-87

Micro Law

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  Richard Stern: Court Dismisses "Copyright Champion's" Source Code Copyright Suit. 88-90

Micro Innovations

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  Philip G. Emma: Patent Claims Revisited: Examiners and Trolls. 94-96

Volume 26, Number 4, July-August 2006

Editor-in-Chief's Message

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  Pradip Bose: Pre-Silicon Modeling and Analysis: Impact On Real Design. 3

Micro Economics

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  Shane Greenstein: Legislating Entrepreneurship: An Oxymoron? 4, 86

Features

• 
  Timothy Sherwood, Joshua J. Yi: Guest Editors' Introduction: Computer Architecture Simulation and Modeling. 5-7
• 
  Alaa R. Alameldeen, David A. Wood: IPC Considered Harmful for Multiprocessor Workloads. 8-17
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  Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe: SimFlex: Statistical Sampling of Computer System Simulation. 18-31
• 
  Michael Van Biesbrouck, Brad Calder, Lieven Eeckhout: Efficient Sampling Startup for SimPoint. 32-42
• 
  Sudhanva Gurumurthi, Youngjae Kim, Anand Sivasubramaniam: Using STEAM for Thermal Simulation of Storage Systems. 43-51
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  Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi, Steven K. Reinhardt: The M5 Simulator: Modeling Networked Systems. 52-60
• 
  Yong-Joon Park, Zhao Zhang, Gyungho Lee: Microarchitectural Protection Against Stack-Based Buffer Overflow Attacks. 62-71
• 
  Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals: Software Demand, Hardware Supply. 72-82

Micro Review

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  Richard Mateosian: Old and New. 83-85

Micro Innovations

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  Philip G. Emma: The Mechanics of Filing a Patent. 88, 87

Volume 26, Number 5, September-October 2006

Editor-in-Chief's Message

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  Pradip Bose: Designing reliable systems with unreliable components. 5-6

Micro Economics

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  Shane Greenstein: Ubiquitous clicks and complements. 7-8

Micro Law

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  Richard Stern: New Jersey federal court holds Qualcomm's unFRANDly acts no antitrust violation. 9

Features

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  Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt: Using Bulk Built-in Current Sensors to Detect Soft Errors. 10-18
• 
  Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. 19-27
• 
  Radu Teodorescu, Jun Nakano, Josep Torrellas: SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. 28-40
• 
  Ricardo E. Gonzalez: A Software-Configurable Processor Architecture. 42-51
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  Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven: Efficient, Scalable Congestion Management for Interconnection Networks. 52-66
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  Valentina Salapura, Robert Walkup, Alan Gara: Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene. 67-81

Micro Review

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  Richard Mateosian: So many books. 82-83

Micro Innovations

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  Philip G. Emma: Prosecuting your patent. 88, 87

Volume 26, Number 6, November/December 2006

Editor-in-Chief's Message

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  Pradip Bose: Looking briefly back, and then forward... 8-9

Micro Economics

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  Shane Greenstein: Four nightmares for net neutrality. 12-13

Features

• 
  Daniel Gracia Pérez, Hugues Berry, Olivier Temam: A Sampling Method Focusing on Practicality. 14-28
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  Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin: Impact of Parameter Variations on Circuits and Microarchitecture. 30-39
• 
  Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter: Leveraging Wire Properties at the Microarchitecture Level. 40-52

Micro Innovations

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  Philip G. Emma: Five strategies for overcoming obviousness. 70-72