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ORCIDIntegration, Volume 88
Volume 88, January 2023
- Jyoti Kandpal, Tika Ram Pokhrel, Shalu Saini, Alak Majumder
:
A variation resilient keeper design for high performance domino logic applications. 1-9
- Qing Zhang, Yuhang Zhang, Jizuo Li, Yongfu Li:
Corrigendum to "WDP-BNN: Efficient wafer defect pattern classification via binarized neural network" [Integration 85 (2022) 76-86]. 10
- Jayant K. Singh, Garima Kapur:
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain. 11-19 - Chencan Zhou, Jie Qiu, Yang Cao, Geng-Chen Yang, Qin-Qin Shen, Quan Shi:
An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalization. 20-31 - D. Rebecca Florance, B. Prabhakar:
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies. 32-42 - Melvin T. Balakrishnan, T. G. Venkatesh, A. Vijaya Bhaskar:
Design and implementation of congestion aware router for network-on-chip. 43-57 - Shatadal Chatterjee, Sounak Roy:
A low power offset voltage calibration method for flash ADCs. 58-69 - Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat:
SMS-CAM: Shared matchline scheme for content addressable memory. 70-79 - Vasiliki Gogolou, Konstantinos Kozalakis, Thomas Noulis, Stylianos Siskos:
Integrated DC - DC converter design methodology for design cycle speed up. 80-90 - Manal Messadi, Karim Kemih, Lazaros Moysis, Christos K. Volos:
A new 4D Memristor chaotic system: Analysis and implementation. 91-100 - Yunan Zhao, Haomin Hou, Shuhao Zhang, Hao Wang, Sheng Chang, Qijun Huang, Jin He:
A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS. 101-107 - Helen-Maria Dounavi, Yiorgos Tsiatouhas:
An aging monitoring scheme for SRAM decoders. 108-115 - Pingakshya Goswami, Benjamin Carrión Schäfer, Dinesh Bhatia:
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. 116-124 - Sagarika Chowdhury, Ritwika Majumdar, Rajat Kumar Pal, Goutam Saha:
Automated path selection technique while incorporating multiple assay operations and cross-contamination avoidance in cross-referencing DMFBs. 125-138 - Kapil Bhardwaj, Mayank Srivastava:
VDTA and DO-CCII based incremental/decremental floating memductance/meminductance simulator: A novel realization. 139-155
- Satyabrata Sarangi, Bevan M. Baas:
Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs. 156-165
- Liqiang Ding, Xiaowu Cai, Mali Gao, Ruirui Xia, Yuexin Gao:
A high reliability under-voltage lock out circuit for power driver IC. 166-172 - Bhawna Aggarwal, Shireesh Kumar Rai, Anant Sinha:
New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators. 173-184
- Paulo C. Santos, Bruno E. Forlin, Marco A. Z. Alves, Luigi Carro:
Plug N' PIM: An integration strategy for Processing-in-Memory accelerators. 185-195
- Jindong Zhou, Yuyang Chen, Youliang Jing, Pingqiang Zhou:
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs. 196-202
- Shaohui Yan, Lin Li, Binxian Gu, Yu Cui, Jianjian Wang, Jincai Song:
Design of hyperchaotic system based on multi-scroll and its encryption algorithm in color image. 203-221 - Milad Mehri:
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk. 222-232 - Satyam Shukla, Punyesh Kumar Jha, Kailash Chandra Ray:
An energy-efficient single-cycle RV32I microprocessor for edge computing applications. 233-240
- Li Zhang, Qishen Lv, Di Gao, Xian Zhou, Wenchao Meng, Qinmin Yang, Cheng Zhuo:
A fine-grained mixed precision DNN accelerator using a two-stage big-little core RISC-V MCU. 241-248
- Akash Levy, Michael Oduoza, Akhilesh Balasingam, Roger T. Howe, Priyanka Raina:
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing. 249-261
- Lanya Yu, Jinfeng Yan, Xiao Zhao, Jinhui Huang:
A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique. 262-268 - Yuanyuan Si, Hongjun Liu, Mengdi Zhao:
Constructing keyed strong S-Box with higher nonlinearity based on 2D hyper chaotic map and algebraic operation. 269-277 - Didem Erol, Mustafa Berke Yelten:
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process. 278-285 - Wu Zhou, Yiming Ouyang, Jianhua Li, Dongyu Xu:
A transparent virtual channel power gating method for on-chip network routers. 286-297 - Jiangwei Shang, Kun Zhang, Zhan Zhang, Chuanyou Li, Hongwei Liu:
A high-performance convolution block oriented accelerator for MBConv-Based CNNs. 298-312 - Shelja Kaushal, Ashwani K. Rana:
Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell. 313-319 - Mohammad Asyaei:
New partitioned domino circuit for power-efficient wide gates. 320-327 - Chenkai Zhang, Baoxiang Du:
A fast piecewise image encryption scheme combining NC1DNSM and P-Box. 328-342 - Kaluri Praveen Raja, Zeesha Mishra, Pulkit Singh, Bibhudendra Acharya:
Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications. 343-352 - Afshin Khaksari, Omid Akbari, Behzad Ebrahimi:
BEAD: Bounded error approximate adder with carry and sum speculations. 353-361 - Mehrnoosh Vafaei, M. R. Hosseini, Ebrahim Abiri, Mohammad Reza Salehi:
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications. 362-370 - Tiedong Cheng, Ziyu Xiao, Jianping Guo, Lijun Xu:
A low power high area-efficiency NMOS LDO with fast adaptive bias. 371-378 - Navnit Kumar, Manjeet Kumar, Neeta Pandey:
Electronically tunable positive and negative fractional order inductor circuit using single topology. 379-389 - Farnaz Morshedlou, Ali Asghar Orouji, Nassim Ravanshad:
An energy-efficient analog circuit for detecting QRS complexes from ECG signal. 390-399 - Naifeng Jing, Zihan Zhang, Yongshuai Sun, Pengyu Liu, Liyan Chen, Qin Wang, Jianfei Jiang:
Exploiting bit sparsity in both activation and weight in neural networks accelerators. 400-409
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