International Journal of Reconfigurable Computing, Volume 2012
Volume 2012, 2012
Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek: Exploring Many-Core Design Templates for FPGAs and ASICs.- Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow: Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms.
- Sascha Mühlbach, Andreas Koch: A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection.
- Tom Davidson, Fatma Abouelella, Karel Bruneel, Dirk Stroobandt: Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment.
- Kaveh Aasaraai, Andreas Moshovos: NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.
- Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings: A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform.
- Angelo Kuti Lusala, Jean-Didier Legat: Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks.
- Mariusz Grad, Christian Plessl: On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.
- William V. Kritikos, Andrew G. Schmidt, Ron Sass, Erik K. Anderson, Matthew French: Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip.
- Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich: Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures.
- Zain-ul-Abdin, Bertil Svensson: Occam-pi for Programming of Massively Parallel Reconfigurable Architectures.
- Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker: Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices.
- Ali Akbar Zarezadeh, Christophe Bobda: Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras.
- Christian de Schryver, Daniel Schmidt, Norbert Wehn, Elke Korn, Henning Marxen, Anton Kostiuk, Ralf Korn: A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision.
- Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala: Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application.
- Ra Inta, David John Bowman, Susan M. Scott: The "Chimera": An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform.
- Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography.
- Christoph Starke, Vasco Grossmann, Lars Wienbrandt, Sven Koschnicke, John Carstens, Manfred Schimmler: Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA.
- Florent Bernard, Viktor Fischer, Crina Costea, Robert Fouquet: Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response.
- Juan Fernando Eusse Giraldo, Nahri Moreano, Alba Cristina Magalhaes Alves de Melo, Ricardo Pezzuol Jacobi: A Protein Sequence Analysis Hardware Accelerator Based on Divergences.
- Lu Wan, Chen Dong, Deming Chen: A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance.
- Andrew G. Schmidt, William V. Kritikos, Shanyuan Gao, Ron Sass: An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing.
- Khaled Benkrid, Ali Akoglu, Cheng Ling, Yang Song, Ying Liu, Xiang Tian: High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP.
- Esam El-Araby, Ivan Gonzalez, Sergio López-Buedo, Tarek A. El-Ghazawi: A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers.
- Kamana Sigdel, Carlo Galuzzi, Koen Bertels, Mark Thompson, Andy D. Pimentel: Evaluation of Runtime Task Mapping Using the rSesame Framework.
- Khaled Benkrid, Esam El-Araby, Miaoqing Huang, Kentaro Sano, Thomas Steinke: High-Performance Reconfigurable Computing.
- Jones Yudi Mori, Janier Arias-Garcia, Camilo Sánchez-Ferreira, Daniel M. Muñoz, Carlos Humberto Llanos Quintero, José Mauricio S. T. Motta: An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots.
- Alba Sandyra Bezerra Lopes, Ivan Saraiva Silva, Luciano Volcan Agostini: A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos.
- Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Wang Jiang Chau, Marius Strum: QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection.
- Alexander Thomas, Michael Rückauer, Jürgen Becker: HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture.
- David Castells-Rufas, Eduard Fernandez-Alonso, Jordi Carrabina: Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems.
- Supriya Aggarwal, Kavita Khare: Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency.
- David H. K. Hoe, Jonathan M. Comer, Juan C. Cerda, Chris D. Martinez, Mukul V. Shirvaikar: Cellular Automata-Based Parallel Random Number Generators Using FPGAs.
- Wilmar Carvajal Ossa, Wilhelmus A. M. Van Noije: An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H.
- Matthias Kühnle, André Wagner, Alisson Vasconcelos De Brito, Jürgen Becker: Modeling and Implementation of a Power Estimation Methodology for SystemC.
- Daniel Palomino, Guilherme Corrêa, Cláudio Machado Diniz, Sergio Bampi, Luciano Volcan Agostini, Altamiro Amadeu Susin: Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
- Christoph Roth, Joachim Meyer, Michael Rückauer, Oliver Sander, Jürgen Becker: Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels.
- Claudia Feregrino, Miguel Arias, Kris Gaj, Viktor K. Prasanna, Marco D. Santambrogio, Ron Sass: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10).
- Gustavo Sanchez, Felipe Sampaio, Marcelo Schiavon Porto, Sergio Bampi, Luciano Volcan Agostini: DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation.
- Hanaa M. Hussain, Khaled Benkrid, Ali Ebrahim, Ahmet T. Erdogan, Huseyin Seker: Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs.
- Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner: Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration.
- Rafael A. Arce-Nazario, José R. Ortiz-Ubarri: Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs.
- Lyndon Judge, Suvarna Mane, Patrick Schaumont: A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication.
- Andrew G. Schmidt, Neil Steiner, Matthew French, Ron Sass: HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs.
- Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak, Weiler Alves Finamore, Manfred Glesner: A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme.
- Michael Schaeferling, Ulrich Hornung, Gundolf Kiefer: Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic.
- Zoltán Endre Rákossy, Zheng Wang, Anupam Chattopadhyay: High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures.
- Eduardo Romero-Aguirre, Ramon Parra-Michel, Roberto Carrasco-Alvarez, Aldo G. Orozco-Lugo: Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems.
- George Sobral Silveira, Alisson Vasconcelos De Brito, Helder F. de A. Oliveira, Elmar U. K. Melcher: Open SystemC Simulator with Support for Power Gating Design.
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last updated on 2013-06-18T214307 by the dblp team