6. SLIP 2004: Paris, France

Louis Scheffer, Igor L. Markov (Eds.): The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings. ACM 2004, ISBN 1-58113-818-0

Interconnect analysis for SoCs and microprocessors

Reinaldo A. Bergamaschi:
Early and accurate analysis of SoCs: oxymoron or real? 3-6
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir:
Interconnect-power dissipation in a microprocessor. 7-13

Models and metrics of interconnect performance

Bipin Rajendran, Pawan Kapur, Krishna Saraswat, R. Fabian, W. Pease:
Self-consistent power/performance/reliability analysis for copper interconnects. 17-22
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Investigation of performance metrics for interconnect stack architectures. 23-29
Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. 31-38

Interconnect design and optimization

Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex:
Interconnect width selection for deep submicron designs using the table lookup method. 41-44
Vikas Chandra, Anthony Xu, Herman Schmit:
A low power approach to system level pipelined interconnect design. 45-52
Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi:
Topology optimization for application-specific networks-on-chip. 53-60

Interconnect in communication networks

Dmitri B. Chklovskii:
Evolution as the blind engineer: wiring minimization in the brain. 63
Ajay Joshi, Jeffrey A. Davis:
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). 64-68
Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson:
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. 69-75

Unconventional interconnects

Ian O'Connor:
Optical solutions for system-level interconnect. 79-88
Arvind Kumar, Sandip Tiwari:
Defect tolerance for nanocomputer architecture. 89-96

Statistical interconnect prediction

Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix:
Prediction of interconnect adjacency distribution: derivation, validation, and applications. 99-106
Tao Wan, Malgorzata Chrzanowska-Jeske:
Prediction of interconnect net-degree distribution based on Rent's rule. 107-114
Maurizio Martina, Guido Masera:
A statistical model for estimating the effect of process variations on crosstalk noise. 115-120

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