ICSAMOS 2008: Samos, Greece

Keynotes

• Trevor N. Mudge:
  PicoServer - building a compact energy efficient multiprocessor.
  
• Tor E. Jeremiassen:
  Challenges in embedded system simulation.
  
• Manolis Katevenis:
  Towards unified mechanisms for inter-processor communication.
  

Embedded Parallel Systems

• Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang:
  A general model of concurrency and its implementation as many-core dynamic RISC processors. 1-9
  
• Yuan Lin, Yoonseo Choi, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti:
  A parameterized dataflow language extension for embedded streaming systems. 10-17
  
• Jonathan Barre, Christine Rochange, Pascal Sainrat:
  An architecture for the simultaneous execution of hard real-time threads. 18-24
  
• Konstantinos Nikas, Matthew Horsnell, Jim D. Garside:
  An adaptive bloom filter cache partitioning scheme for multicore architectures. 25-32
  

Network on a Chip

• Valeriu Beiu, Basheer A. M. Madappuram, T. Martin McGinnity:
  On brain-inspired hybrid topologies for nano-architectures - a Rent's rule approach -. 33-40
  
• Heiner Giefers, Marco Platzner:
  Realizing reconfigurable mesh algorithms on softcore arrays. 41-48
  
• Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
  A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. 49-56
  

Design Space Exploration

• Ben Cope, Peter Y. K. Cheung, Wayne Luk:
  Systematic design space exploration for customisable multi-processor architectures. 57-64
  
• Carlo Galuzzi, Dimitris Theodoropoulos, Koen Bertels:
  Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions. 65-73
  
• Michael Glaß, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich:
  Multi-objective routing and topology optimization in networked embedded systems. 74-81
  

Applications

• Christos Strydis, Christoforos Kachris, Georgi Gaydadjiev:
  ImpBench: A novel benchmark suite for biomedical, microelectronic implants. 82-91
  
• Holger Blume, M. Haller, Martin Botteck, Wolfgang M. Theimer:
  Perceptual feature based music classification - A DSP perspective for a new type of application. 92-99
  
• Janne Janhunen, Olli Silvén, Markku J. Juntti, Markus Myllylä:
  Software defined radio implementation of K-best list sphere detector algorithm. 100-107
  

Processor Architecture

• Juho Antikainen, Perttu Salmela, Olli Silvén, Markku J. Juntti, Jarmo Takala, Markus Myllylä:
  Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm. 108-115
  
• Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos:
  An instruction set extension for java bytecodes translation acceleration. 116-123
  
• Mohammad A. Makhzan, Ahmed M. Eltawil, Fadi J. Kurdahi:
  Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices. 124-131
  
• Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Xinmin Tian, Milind Girkar, Hideki Saito, Utpal Banerjee:
  Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core^TM 2 Duo processor. 132-141
  

Multiprocessors

• Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi:
  Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems. 142-149
  
• Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
  An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods. 150-157
  
• M. M. Waliullah, Per Stenström:
  Efficient management of speculative data in hardware transactional memory systems. 158-164
  
• Alexandre Chureau, Frédéric Pétrot:
  An intermediate format for automatic generation of MPSoC virtual prototypes. 165-172
  

Reconfigurable Computing

• Giovanni Busonera, Alessandro Forin, Richard Neil Pittman:
  Exploiting partial reconfiguration for flexible software debugging. 173-181
  
• Markus Rullmann, Renate Merker:
  A cost model for partial dynamic reconfiguration. 182-186
  
• William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer:
  Reconfigurable design with clock gating. 187-194
  

Memory and Caches

• Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum:
  A centralized cache miss driven technique to improve processor power dissipation. 195-202
  
• Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou:
  A priority-expression-based burst scheduling of memory reordering access. 203-209
  
• Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf:
  Improving memory subsystem performance in network processors with smart packet segmentation. 210-217
  
• Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee:
  Improving TLB energy for java applications on JVM. 218-223
  

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