ISPD 2004: Phoenix, Arizona, USA

• Robert K. Montoye:
  The four degrees of 3D. 1
  

Placement Techniques

• Ulrich Brenner, Anna Pauli, Jens Vygen:
  Almost optimum placement legalization by minimum cost flow and dynamic programming. 2-9
  
• Haoxing Ren, David Zhigang Pan, David S. Kung:
  Sensitivity guided net weighting for placement driven synthesis. 10-17
  
• Andrew B. Kahng, Qinke Wang:
  Implementation and extensibility of an analytic placer. 18-25
  
• Natarajan Viswanathan, Chris C. N. Chu:
  FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. 26-33
  

Routing Topology Optimization

• Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
  Multilevel routing with antenna avoidance. 34-40
  
• Hua Xiang, Kai-Yuan Chao, D. F. Wong:
  An ECO algorithm for eliminating crosstalk violations. 41-46
  
• Charles J. Alpert, Milos Hrkic, Stephen T. Quay:
  A fast algorithm for identifying good buffer insertion candidate locations. 47-52
  
• Dennis K. Y. Tong, Evangeline F. Y. Young:
  Performance-driven register insertion in placement. 53-60
  

Panel: Buffering and Agony: What does the future hold?

• Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester:
  The great interconnect buffering debate: are you a chicken or an ostrich? 61
  

Floorplanning

• Mario R. Casu, Luca Macchiarulo:
  Floorplanning for throughput. 62-69
  
• Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky:
  Multi-project reticle floorplanning and wafer dicing. 70-77
  
• Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl:
  An area-optimality study of floorplanning. 78-83
  
• Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden:
  Recursive bisection based mixed block placement. 84-89
  

Regular Circuit Fabrics: Act Two - the Industrial Perspectives

• Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda:
  Design methodology and tools for NEC electronics' structured ASIC ISSP. 90-96
  
• Deepak D. Sherlekar:
  Design considerations for regular fabrics. 97-102
  
• Kun-Cheng Wu, Yu-Wen Tsai:
  Structured ASIC, evolution or revolution? 103-106
  

3D-Design

• Robert K. Montoye:
  The four degrees of 3D. 107
  
• Shamik Das, Andy Fan, Kuan-Neng Chen, Chuan Seng Tan, Nisha Checka, Rafael Reif:
  Technology, performance, and computer-aided design of three-dimensional integrated circuits. 108-115
  

Power Optimization

• Jaskirat Singh, Sachin S. Sapatnekar:
  Topology optimization of structured power/ground networks. 116-123
  
• Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
  Sensitivity guided net weighting for placement driven synthesis. 124-131
  
• Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
  Early-stage power grid analysis for uncertain working modes. 132-137
  

Clock

• Monica Donno, Enrico Macii, Luca Mazzoni:
  Power-aware clock tree planning. 138-147
  

FPGA

• Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh:
  Innovate or perish: FPGA physical design. 148-155
  

Parasitic Analysis and Control

• Changbo Long, Jinjun Xiong, Lei He:
  On optimal physical synthesis of sleep transistors. 156-161
  
• Rafael Escovar, Salvador Ortiz, Roberto Suaya:
  Mutual inductance extraction and the dipole approximation. 162-169
  
• Lakshmi Kalpana Vakati, Janet Meiling Wang:
  A new multi-ramp driver model with RLC interconnect load. 170-175
  
• Debjit Sinha, Hai Zhou, Chris C. N. Chu:
  Optimal gate sizing for coupling-noise reduction. 176-181
  
• Kai Wang, Malgorzata Marek-Sadowska:
  Clock network sizing via sequential linear programming with time-domain analysis. 182-189
  

Design Styles

• Peter J. Osler:
  Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. 190-197
  

Statistical Analysis for Placement

• Qinghua Liu, Malgorzata Marek-Sadowska:
  A study of netlist structure and placement efficiency. 198-203
  
• Jurjen Westra, Chris Bartels, Patrick Groeneveld:
  Probabilistic congestion prediction. 204-209
  
• Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
  A predictive distributed congestion metric and its application to technology mapping. 210-217
  

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