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ORCID19th ISCA 1992: Gold Coast, Queensland, Australia
- Allan Gottlieb:
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992. ACM 1992, ISBN 0-89791-509-7 - Richard N. Zucker, Jean-Loup Baer:
A Performance Study of Memory Consistency Models. 2-12 - Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel:
Lazy Release Consistency for Software Distributed Shared Memory. 13-21 - Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy:
Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors. 22-33 - Edil S. T. Fernandes, Fernando M. B. Barbosa:
Effects of Building Blocks on the Performance of Super-Scalar Architectures. 36-45 - Monica S. Lam, Robert P. Wilson:
Limits of Control Flow on Parallelism. 46-57 - Manoj Franklin, Gurindar S. Sohi:
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. 58-67 - Daniel Litaize, Abdelaziz Mzoughi, Christine Rochange, Pascal Sainrat:
Towards a Shared-Memory Massively Parallel Multiprocessor. 70-79 - Per Stenström, Truman Joe, Anoop Gupta:
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. 80-91 - Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, John L. Hennessy:
The DASH Prototype: Implementation and Performance. 92-103 - Gideon D. Intrater, Ilan Y. Spillinger:
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. 106-113 - J. Bradley Chen, Anita Borg, Norman P. Jouppi:
A Simulation Based Study of TLB Performance. 114-123 - Tse-Yu Yeh, Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction. 124-134 - Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yoshiyuki Mochizuki, Akio Nishimura, Yoshimori Nakase, Teiji Nishizawa:
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. 136-145 - Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai
, Yoshinori Yamaguchi, Yasuhito Koumura:
Thread-based Programming for the EM-4 Hybrid Dataflow Machine. 146-155 - Rishiyur S. Nikhil, Gregory M. Papadopoulos, Arvind:
*T: A Multithreaded Massively Parallel Architecture. 156-167 - Cezary Dubnicki, Thomas J. LeBlanc:
Adjustable Block Size Coherent Caches. 170-180 - Kunle Olukotun, Trevor N. Mudge, Richard B. Brown:
Performance Optimization of Pipelined Primary Caches. 181-190 - Scott McFarling:
Cache Replacement with Dynamic Exclusion. 191-200 - Stephen W. Keckler, William J. Dally:
Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. 202-213 - Bob Boothe, Abhiram G. Ranade:
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors. 214-223 - Alessandro De Gloria, Paolo Faraboschi:
Instruction-level Parallelism in Prolog: Analysis and Architectural Support. 224-233 - Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor:
Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. 236-245 - André Seznec, Jacques Lenfant:
Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers. 246-255 - Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, Klaus E. Schauser:
Active Messages: A Mechanism for Integrated Communication and Computation. 256-266 - Andrew A. Chien, Jae H. Kim:
Planar-Adaptive Routing: Low-cost Adaptive Networks for Multiprocessors. 268-277 - Christopher J. Glass, Lionel M. Ni:
The Turn Model for Adaptive Routing. 278-287 - Toshiyuki Shimizu, Takeshi Horie, Hiroaki Ishihata:
Low-Latency Message Communication Support for the AP1000. 288-297 - Barbara P. Aichinger:
Futurebus+ as an I/O Bus: Profile B. 300-307 - A. L. Narasimha Reddy:
A Study of I/O System Organizations. 308-317 - Jai Menon, Dick Mattson:
Comparison of Sparing Alternatives for Disk Arrays. 318-329 - Markus Siegle, Richard Hofmann:
Monitoring Program Behaviour on SUPRENUM. 332-341 - Todd M. Austin, Gurindar S. Sohi:
Dynamic Dependency Analysis of Ordinary Programs. 342-351 - Walid A. Najjar, William Marcus Miller, A. P. Wim Böhm:
An Analysis of Loop Latency in Dataflow Execution. 352-360 - Qing Yang, Liping Wu Yang:
A Novel Cache Design for Vector Processing. 362-371 - Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro:
Increasing the Number of Strides for Conflict-Free Vector Access. 372-381 - William A. Wulf:
Evaluation of the WM Architecture. 382-390 - Kirk L. Johnson:
The Impact of Communication Locality on Large-Scale Multiprocessor Performance. 392-402 - Steven L. Scott, James R. Goodman, Mary K. Vernon:
Performance of the SCI Ring. 403-414 - Madhusudhan Talluri, Shing I. Kong, Mark D. Hill, David A. Patterson:
Tradeoffs in Supporting Two Page Sizes. 415-424
Abstracts
- André Seznec, Karl Courtel:
OPAC: A floating-point coprocessor dedicated to compute-bound kernels. 427 - Ahmed Louri, Jongwhoa Na:
Parallel electro-optical rule-based system for fast execution of expert systems. 427 - Ahmed Louri, Hongki Sung:
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. 428 - Der-Chung Cheng, Kanad Ghose:
The time-constrained barrier synchronizer and its applications in parallel systems. 428 - Ruben Yomtov:
Performance evaluation of disk subsystems. 429 - Gautam B. Singh:
Architecture of a graphics processor. 429 - Feipei Lai, Meng-chou Chang:
Enhancing boosting with semantic register in a superscalar processor. 430 - Ivan Sklenár:
Prefetch unit for vector operations on scalar computers. 430 - Gary Newman:
Memory management support for tiled array organization. 431 - Augustus K. Uht, Darin B. Johnson:
Data path issues in a highly concurrent machine. 431 - Samuel A. Fineberg, Thomas L. Casavant, Brent H. Pease:
Seamless - a latency-tolerant RISC-based multiprocessor architecture. 432 - Mohammed Azhar Sayeed, Mohammed Atiquzzaman:
Performance of multiple-bus multiprocssor under non-uniform memory reference model. 432 - Anujan Varma, Gunjan Sinha:
A class of prefetch schemes for on-chip data caches. 433 - M. Tahar Kechadi, Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux:
Performance improvement for vector pipeline multiprocessor systems using a disordered execution model. 433 - Arthur Abnous, Nader Bagherzadeh:
Pipelining and bypassing in a VLIW processor. 434 - Shiv Prakash, Alice C. Parker:
Synthesis of application-specific heterogeneous multiprocessor systems. 434 - Matthew K. Farrens, Arvin Park, Rob Fanfelle, Pius Ng, Gary S. Tyson:
A partitioned translation lookaside buffer approach to reducing address bandwith. 435 - James Laudon, Anoop Gupta, Mark Horowitz:
Architectural and implementation tradeoffs in the design of multiple-context processors. 435 - Jaswinder Pal Singh:
Implications of hierarchical N-body methods for multiprocessor architecture. 436 - Brian D. Alleyne, Isaac D. Scherson:
Expanded delta networks for very large parallel computers. 436 - Wen-Hann Wang, Jim Quinlan, Konrad Lai:
Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches. 437 - Wisam Michael:
Directory-based cache coherency protocol for a ring-connected multiprocessor-array. 437 - Craig M. Wittenbrink, Arun K. Somani, C. H. Chen:
Cache write generate for high performance parallel processing. 438 - David E. Culler, Michial A. Gunter, James C. Lee:
Analysis of multithreaded microprocessors under multiprogramming. 438 - Walter H. Burkhardt, Stefan Rust:
Integrated computer architecture development system. 439
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