7. HPCA 2001: Nuevo Leone, Mexico

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001. IEEE Computer Society 2001, ISBN 0-7695-1019-1

Microarchitecture I

Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson:
Stack Value File: Custom Microarchitecture for the Stack. 5-14
Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen:
Register Renaming and Scheduling for Dynamic Execution of Predicated Code. 15-25
Pierre Michaud, André Seznec:
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. 27-36
Amir Roth, Gurindar S. Sohi:
Speculative Data-Driven Multithreading. 37-48

Memory Architectures

Xiaogang Qiu, Michel Dubois:
Towards Virtually-Addressed Memory Hierarchies. 51-62
Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sally A. McKee:
Reevaluating Online Superpage Promotion with Hardware Support. 63-72
Bülent Abali, Hubertus Franke, Xiaowei Shen, Dan E. Poff, T. Basil Smith:
Performance of Hardware Compressed Main Memory. 73-81

Multiprocessor Systems

Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary:
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. 85-96
Manuel E. Acacio, José González, José M. García, José Duato:
A New Scalable Directory Architecture for Large-Scale Multiprocessors. 97-106
Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee:
Self-Tuned Congestion Control for Multiprocessor Networks. 107-118

Code Generation Techniques

Jaejin Lee, Yan Solihin, Josep Torrellas:
Automatically Mapping Code on an Intelligent Memory Architecture. 121-132
Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala:
CARS: A New Code Generation Framework for Clustered ILP Processors. 133-143

Energy and Thermal Management

Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. 147-157
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin:
DRAM Energy Management Using Software and Hardware Directed Power Mode Control. 159-169
David Brooks, Margaret Martonosi:
Dynamic Thermal Management for High-Performance Microprocessors. 171-182

Prediction Techniques

Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder:
Dynamic Prediction of Critical Path Instructions. 185-195
Daniel A. Jiménez, Calvin Lin:
Dynamic Branch Prediction with Perceptrons. 197-206
Bart Goeman, Hans Vandierendonck, Koenraad De Bosschere:
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency. 207-216

Application-Specific Designs

Jesús Corbal, Roger Espasa, Mateo Valero:
DLP + TLP Processors for the Next Generation of Media Workloads. 219-228
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko H. Lipasti:
An Architectural Evaluation of Java TPC-W. 229-240
Craig B. Zilles, Gurindar S. Sohi:
A Programmable Co-Processor for Profiling. 241-252

Performance Modeling and Analysis

Li-Shiuan Peh, William J. Dally:
A Delay Model and Speculative Architecture for Pipelined Routers. 255-266
Taliver Heath, Samian Kaur, Richard P. Martin, Thu D. Nguyen:
Quantifying the Impact of Architectural Scaling on Communication. 267-277

Latency Tolerance Techniques

Murali Annavaram, Jignesh M. Patel, Edward S. Davidson:
Call Graph Prefetching for Database Applications. 281-290
Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak:
Branch History Guided Instruction Prefetching. 291-300
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger:
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. 301-312

Workshops

Tutorials

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