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ORCID17th COOL Chips 2014: Yokohama, Japan
- 2014 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVII, Yokohama, Japan, April 14-16, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-3810-0
- Jun'ichi Segawa, Yusuke Shirota, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai:
Aggressive use of Deep Sleep mode in low power embedded systems. 1-3 - Gyeonghoon Kim, Seongwook Park, Kyuho Jason Lee, Youchang Kim
, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Junyoung Park, Hoi-Jun Yoo:
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler. 1-3 - Gaku Nakagawa, Shuichi Oikawa:
Language runtime support for NVM/DRAM hybrid main memory. 1-3 - Yunyun Jiang, Yi Yang, Tian Xiao, Tianwei Sheng, Wenguang Chen:
Kernel data race detection using debug register in Linux. 1-3 - Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka:
A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit. 1-3 - Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
An energy optimization method for vector processing mechanisms. 1-3 - Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki, Wataru Uesugi, Takuro Ohmaru, Kazuaki Ohshima, Hidetomo Kobayashi, Seiichi Yoneda, Atsuo Isobe, Naoaki Tsutsui, Suguru Hondo, Yasutaka Suzuki, Yutaka Okazaki, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Gensuke Goto, Masahiro Fujita, James Myers, Pekka Korpinen, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki:
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. 1-3 - Hiroaki Kobayashi:
Message from the organizing committee chair. i-ii - Makoto Ikeda, Fumio Arakawa:
Message from the program committee chairs. iv-v - Masaki Kondo, Fumio Arakawa, Masato Edahiro:
Establishing a standard interface between multi-manycore and software tools - SHIM. 1-3 - Ying Wang, Yinhe Han, Huawei Li:
A low power DRAM refresh control scheme for 3D memory cube. 1-3 - Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura:
A low power NoC router using the marching memory through type. 1-3 - Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro:
Parallel design of control systems utilizing dead time for embedded multicore processors. 1-3 - Fumio Arakawa:
Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve? 1-2 - Yuttakon Yuttakonkit, Jun Yao, Yasuhiko Nakashima:
A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration. 1-3 - Tadao Nakamura:
Message from the advisory committee chair. iii - Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa:
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. 1-3 - Motoki Wada, Mikiko Sato, Mitaro Namiki:
A fine grained power management supported by just-in-time compiler. 1-3
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