PACT 2006: Seattle, Washington, USA

Erik R. Altman, Kevin Skadron, Benjamin G. Zorn (Eds.): 15th International Conference on Parallel Architecture and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006. ACM 2006, ISBN 1-59593-264-X

Jeffrey Dean:
Experiences with MapReduce, an abstraction for large-scale computation. 1

Multi-core design I

Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi:
Architectural support for operating system-driven CMP cache management. 2-12
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. Iyer, Srihari Makineni:
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. 13-22
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi:
Core architecture optimization for heterogeneous chip multiprocessors. 23-32

Program analysis and optimization

Abhishek Das, William J. Dally, Peter R. Mattson:
Compiling for stream processing. 33-42
Silvius Rus, Guobin He, Christophe Alias, Lawrence Rauchwerger:
Region array SSA. 43-52
Kyungwoo Lee, Samuel P. Midkiff:
A two-phase escape analysis for parallel java programs. 53-62
Steve Scott:
Challenges and opportunities in the post single-thread-processor era. 63

Security and correctness

Sumeet Kumar, Aneesh Aggarwal:
Self-checking instructions: reducing instruction redundancy for concurrent error detection. 64-73
Lan Gao, Jun Yang, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee:
A low-cost memory remapping scheme for address bus protection. 74-83
Brian Rogers, Milos Prvulovic, Yan Solihin:
Efficient data protection for distributed shared memory multiprocessors. 84-94

Characterizing program behavior

Ted Huffmire, Timothy Sherwood:
Wavelet-based phase classification. 95-104
Chang-Burm Cho, Tao Li:
Complexity-based program phase analysis and classification. 105-113
Kenneth Hoste, Aashish Phansalkar, Lieven Eeckhout, Andy Georges, Lizy Kurian John, Koen De Bosschere:
Performance prediction based on inherent program similarity. 114-122
Ajay K. Royyuru:
Deep computing in biology: challenges and progress. 123

Multi-core design II

Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Hardware support for spin management in overcommitted virtual machines. 124-133
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi, Austen McDonald, Christos Kozyrakis, Kunle Olukotun:
Testing implementations of transactional memory. 134-143
Ilya Ganusov, Martin Burtscher:
Efficient emulation of hardware prefetchers via event-driven helper threading. 144-153

Performance profiling and tuning

Qin Zhao, Joon Edward Sim, Weng-Fai Wong, Larry Rudolph:
DEP: detailed execution profile. 154-163
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hundt:
Whole-program optimization of global variable layout. 164-172
Zhelong Pan, Rudolf Eigenmann:
Fast, automatic, procedure-level performance tuning. 173-181

Instruction fetch and control flow

Andrew Petersen, Andrew Putnam, Martha Mercaldi, Andrew Schwerin, Susan J. Eggers, Steven Swanson, Mark Oskin:
Reducing control overhead in dataflow architectures. 182-191
Chengmo Yang, Alex Orailoglu:
Power-efficient instruction delivery through trace reuse. 192-201
Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero:
Branch predictor guided instruction decoding. 202-211

Application-specific optimizations

Kaushik Rajan, Ramaswamy Govindarajan:
Two-level mapping based cache index selection for packet forwarding engines. 212-221
Sung-Chul Han, Franz Franchetti, Markus Püschel:
Program generation for the all-pairs shortest path problem. 222-232
Qingda Lu, Sriram Krishnamoorthy, P. Sadayappan:
Combining analytical and empirical approaches in tuning matrix transposition. 233-242
David B. Kirk:
Processor architecture: too much parallelism? 243

Out-of-order microarchitecture

Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev:
Adaptive reorder buffers for SMT processors. 244-253
Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau:
SEED: scalable, efficient enforcement of dependences. 254-264
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. 265-274

Dependences and register allocation

Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir:
Overlapping dependent loads with addressless preload. 275-284
Ivan D. Baev, Richard E. Hank, David H. Gross:
Prematerialization: reducing register pressure for free. 285-294
Johnnie Birch, Robert A. van Engelen, Kyle A. Gallivan, Yixin Shou:
An empirical evaluation of chains of recurrences for array dependence testing. 295-304

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