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Publication search results
found 130 matches
- 1988
- Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland:
Logic design verification via test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 138-148 (1988) - Sheldon B. Akers:
A parity bit signature for exhaustive testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 333-338 (1988) - Amir Alon, Uri M. Ascher:
Model and solution strategy for placement of rectangular blocks in the Euclidean plane. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 378-386 (1988) - Antonio R. Alvarez, Behrooz L. Abdi, Dennis L. Young, Harrison D. Weed, Jim Teplik, Eric R. Herald:
Application of statistical design and response surface methods to computer-aided VLSI device design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(2): 272-288 (1988) - Andrew W. Appel:
Simulating digital circuits with one bit per wire. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 987-993 (1988) - Takao Asano:
Generalized Manhattan path algorithm with applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(7): 797-804 (1988) - M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia:
Allocation of multiport memories in data path synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4): 536-540 (1988) - James A. Barby, Jirí Vlach, Kishore Singhal:
Polynomial splines for MOSFET model approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5): 557-566 (1988) - Erich Barke:
Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(2): 295-298 (1988) - Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 723-740 (1988) - Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 838-849 (1988) - Jan J. H. van der Biesen, Toru Toyabe:
Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 855-861 (1988) - Bernhard E. Boser, Klaus-Peter Karmann, Horst Martin, Bruce A. Wooley:
Simulating and testing oversampled analog-to-digital converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 668-674 (1988) - Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma:
Techniques for multilayer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 698-712 (1988) - Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen:
Macromodeling CMOS circuits for timing simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1237-1249 (1988) - Wolfgang O. Budde:
Modular testprocessor for VLSI chips and high-density PC boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1118-1124 (1988) - Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto:
ESTA: an expert system for DFT rule verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11): 1172-1180 (1988) - Larry Carter, Leendert M. Huisman, Tom W. Williams:
TRIM: testability range by ignoring the memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 38-49 (1988) - Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli:
A new aggregation technique for the solution of large systems of algebraic equations [IC simulation]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 976-986 (1988) - Shek-Wayne Chan, Chin-Long Wey:
The design of concurrent error diagnosable systolic arrays for band matrix multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 21-37 (1988) - D. Y. Cheng, Chang G. Hwang, Robert W. Dutton:
PISCES-MC: a multiwindow, multimethod 2-D device simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 1017-1026 (1988) - Hwan Gue Cho, C. M. Kyung:
A heuristic standard cell placement algorithm using constrained multistage graph model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11): 1205-1214 (1988) - Salim U. Chowdhury, Melvin A. Breuer:
Optimum design of IC power/ground nets subject to reliability constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(7): 787-796 (1988) - Ernst Christen, Jirí Vlach:
NETOPT-a program for multiobjective design of linear networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5): 567-577 (1988) - Edmund M. Clarke, Yulin Feng:
Escher-a geometrical layout system for recursively defined circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 908-918 (1988) - James P. Cohoon, Patrick L. Heck:
BEAVER: a computational-geometry-based tool for switchbox routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 684-697 (1988) - Jason Cong, Martin D. F. Wong, C. L. Liu:
A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1094-1104 (1988) - Christian H. Corbex, Anne F. Gerodelle, Serge P. Martin, Alain R. Poncet:
Data structuring for process and device simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4): 489-500 (1988) - Ronald J. Cosentino:
Concurrent error correction in systolic architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 117-125 (1988) - William M. Coughran Jr., Mark R. Pinto, R. Kent Smith:
Computation of steady-state CMOS latchup characteristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(2): 307-323 (1988)
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retrieved on 2024-05-04 15:50 CEST from data curated by the dblp team
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