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Publication search results
found 50 matches
- 1996
- Saman Adham, Sanjay Gupta:
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. Asian Test Symposium 1996: 205-212 - Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin:
Redundancy Identification Using Transitive Closure. Asian Test Symposium 1996: 4-9 - Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki:
A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. Asian Test Symposium 1996: 263-268 - Jwu E. Chen:
Yield Improvement by Test Error Cancellation. Asian Test Symposium 1996: 258-262 - Kwang-Ting Cheng:
Built-In Self Test for Analog and Mixed-Signal Designs. Asian Test Symposium 1996: 197-198 - Yoon-Hwa Choi, Pong-Gyou Lee:
Concurrent Error Detection and Fault Location in a Fast ATM Switch. Asian Test Symposium 1996: 113-118 - Serge N. Demidenko, Vincenzo Piuri:
On-Line Testing In Digital Neural Networks. Asian Test Symposium 1996: 295- - Christopher P. Fuhrman, Henri J. Nussbaumer:
Comparison Diagnosis in Large Multiprocessor Systems. Asian Test Symposium 1996: 244- - Ad J. van de Goor, Georgi Gaydadjiev:
Realistic Linked Memory Cell Array Faults. Asian Test Symposium 1996: 183-188 - Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer:
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. Asian Test Symposium 1996: 148- - Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99 - Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. Asian Test Symposium 1996: 50-55 - Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka:
A Design for testability Method Using RTL Partitioning. Asian Test Symposium 1996: 88-93 - Po-Ching Hsu, Sying-Jyan Wang:
Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. Asian Test Symposium 1996: 56-61 - Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo:
An Efficient PRPG Strategy By Utilizing Essential Faults. Asian Test Symposium 1996: 199-204 - Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao:
Easily Testable Data Path Allocation Using Input/Output Registers. Asian Test Symposium 1996: 142- - Y.-M. Hur, J.-H. Shin, K.-H. Lee, Y.-S. Son, I.-C. Lim, Y.-H. Kim:
Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing. Asian Test Symposium 1996: 42- - Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara:
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. Asian Test Symposium 1996: 130-135 - Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau:
Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium 1996: 251-257 - Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
On Design of Fail-Safe Cellular Arrays. Asian Test Symposium 1996: 107-112 - Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi:
Formal Verification Of Self-Testing Properties Of Combinational Circuits. Asian Test Symposium 1996: 119-122 - Wuudiann Ke:
Hybrid Pin Control Using Boundary-Scan And Its Applications. Asian Test Symposium 1996: 44-49 - Hisashi Kondo, Kwang-Ting Cheng:
An Efficient Compact Test Generator for IDDQ Testing. Asian Test Symposium 1996: 177-182 - Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano:
A Consistent Scan Design System for Large-Scale ASICs. Asian Test Symposium 1996: 82-87 - Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada:
Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. Asian Test Symposium 1996: 171-176 - Kowen Lai, Christos A. Papachristou:
BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. Asian Test Symposium 1996: 219- - Kuen-Jong Lee, Jing-Jou Tang:
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. Asian Test Symposium 1996: 165-171 - Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium 1996: 100- - Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15 - Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu:
A MISR Computation Algorithm for Fast Signature Simulation. Asian Test Symposium 1996: 213-218
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