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Publication search results
found 193 matches
- 2007
- Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
Parameterized Non-Gaussian Variational Gate Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1495-1508 (2007) - Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler:
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 896-906 (2007) - Sandip Aine, P. P. Chakrabarti, Rajeev Kumar:
An Automated Meta-Level Control Framework for Optimizing the Quality-Time Tradeoff of VLSI Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1992-2008 (2007) - Sultan M. Al-Harbi, Fadel Noor, Fadi M. Al-Turjman:
March DSS: A New Diagnostic March Test for All Memory Simple Static Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1713-1720 (2007) - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda:
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 907-918 (2007) - Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini:
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 421-434 (2007) - Kazuo Aoyama:
Design Methods for Symmetric Function Generators Based on Threshold Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1934-1946 (2007) - Sanghyeon Baeg:
Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2215-2221 (2007) - Kedarnath J. Balakrishnan, Nur A. Touba:
Relationship Between Entropy and Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 386-395 (2007) - Felice Balarin, Roberto Passerone:
Specification, Synthesis, and Simulation of Transactor Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1749-1762 (2007) - Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1331-1339 (2007) - Kia Bazargan, André DeHon:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 201-202 (2007) - Giovanni Beltrame, Donatella Sciuto, Cristina Silvano:
Multi-Accuracy Power and Performance Transaction-Level Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1830-1842 (2007) - Wendemagegnehu T. Beyene:
Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 166-176 (2007) - Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 435-446 (2007) - Bradley N. Bond, Luca Daniel:
A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order Reduction for Highly Nonlinear Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2116-2129 (2007) - Yu Cao, Lawrence T. Clark:
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1866-1873 (2007) - Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 152-165 (2007) - Amitabh Chaudhary, Danny Z. Chen, Xiaobo Sharon Hu, Michael T. Niemier, Ramprasad Ravichandran, Kevin Whitton:
Fabricatable Interconnect and Molecular QCA Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1978-1991 (2007) - Tai-Chen Chen, Yao-Wen Chang:
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1041-1053 (2007) - Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar:
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1139-1149 (2007) - Jun Chen, Lei He:
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 734-738 (2007) - Xiaoyong Chen, Douglas L. Maskell, Yang Sun:
Fast Identification of Custom Instructions for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 359-368 (2007) - Ruiming Chen, Hai Zhou:
An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2069-2073 (2007) - Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1211-1221 (2007) - Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 115-126 (2007) - Youngjin Cho, Naehyuck Chang:
Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1030-1040 (2007) - Sung Jin Cho, Un-Sook Choi, Han-Doo Kim, Yoon-Hee Hwang, Jin-Gyoung Kim, Seong-Hun Heo:
New Synthesis of One-Dimensional 90/150 Linear Hybrid Group Cellular Automata. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1720-1724 (2007) - Minsik Cho, David Z. Pan:
BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2130-2143 (2007) - Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy:
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2059-2068 (2007)
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