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Publication search results
found 25 matches
- 2018
- Armineh Arasteh, Mohammad Hossein Moaiyeri
, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh
:
An energy and area efficient 4: 2 compressor based on FinFETs. Integr. 60: 224-231 (2018) - Sana Arshad, Rashad Ramzan, Qamar-ul-Wahab:
50-830 MHz noise and distortion canceling CMOS low noise amplifier. Integr. 60: 63-73 (2018) - Mohammad Asyaei:
A new low-power dynamic circuit for wide fan-in gates. Integr. 60: 263-271 (2018) - Urvashi Bansal, Maneesha Gupta
:
High bandwidth transimpedance amplifier using FGMOS for low voltage operation. Integr. 60: 153-159 (2018) - Rupam Bhattacharya
, Pranab Roy, Hafizur Rahaman
:
Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation. Integr. 60: 74-91 (2018) - Qiang Han, Qiang Xu
, Wen-Ben Jone:
SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits. Integr. 60: 1-12 (2018) - Mohsen Hayati, Sajad Cheraghaliei, Sepehr Zarghami:
Design of UWB low noise amplifier using noise-canceling and current-reused techniques. Integr. 60: 232-239 (2018) - Jui-Hung Hsieh, Rong-Choi Lee, King-Chu Hung, Meng-Ju Shih:
Rapid and coding-efficient SPIHT algorithm for wavelet-based ECG data compression. Integr. 60: 248-256 (2018) - Ahmad Karimi
, Abdalhossein Rezai, Mohammad Mahdi Hajhashemkhani:
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power. Integr. 60: 160-166 (2018) - Sangmin Kim, Youngsoo Shin:
Module grouping to reduce the area of test wrappers in SoCs. Integr. 60: 39-47 (2018) - M. Kiruba, V. Sumathy:
Register Pre-Allocation based Folded Discrete Tchebichef Transformation Technique for Image Compression. Integr. 60: 13-24 (2018) - Austin Lancaster, Manish Keswani
:
Integrated circuit packaging review with an emphasis on 3D packaging. Integr. 60: 204-212 (2018) - Yanbin Li
, Ming Tang, Yuguang Li, Huanguo Zhang:
Several weaknesses of the implementation for the theoretically secure masking schemes under ISW framework. Integr. 60: 92-98 (2018) - Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay:
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. Integr. 60: 167-189 (2018) - Minho Nam, Kyoung-Rok Cho:
Implementation of real-time image edge detector based on a bump circuit and active pixels in a CMOS image sensor. Integr. 60: 56-62 (2018) - Yiming Ouyang, Jianfeng Yang, Kun Xing, Zhengfeng Huang, Huaguo Liang:
An improved communication scheme for non-HOL-blocking wireless NoC. Integr. 60: 240-247 (2018) - Hitesh Pahuja, Mintu Tyagi, Sudhakar Panday, Balwinder Singh
:
A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations. Integr. 60: 99-116 (2018) - Mohammad Radpour
, Sayed Masoud Sayedi:
SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor. Integr. 60: 48-55 (2018) - Habib Rastegar, Saeid Zare, Jee-Youl Ryu:
A low-voltage low-power capacitive-feedback voltage controlled oscillator. Integr. 60: 257-262 (2018) - Guoyong Shi:
Toward automated reasoning for analog IC design by symbolic computation - A survey. Integr. 60: 117-131 (2018) - Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta
:
Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. Integr. 60: 25-38 (2018) - Sheldon X.-D. Tan, Hussam Amrouch
, Taeyoung Kim
, Zeyu Sun, Chase Cook, Jörg Henkel:
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited). Integr. 60: 132-152 (2018) - Mehmet Tükel, Arda Yurdakul, Berna Örs
:
Customizable embedded processor array for multimedia applications. Integr. 60: 213-223 (2018) - Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai:
Asymmetry dual-LFSR reseeding for low power BIST. Integr. 60: 272-276 (2018) - Ailin Zhang, Guoyong Shi:
A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization. Integr. 60: 190-203 (2018)
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retrieved on 2024-08-27 23:36 CEST from data curated by the dblp team
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